Commit 3086ae07 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'arc-5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC fixes from Vineet Gupta:

 - Fix __ALIGN_STR and __ALIGN to not use default junk padding

 - Misc Kconfig cleanups, header updates

* tag 'arc-5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: define __ALIGN_STR and __ALIGN symbols for ARC
  ARC: show_regs: reduce lines of output
  ARC: Replace <linux/clk-provider.h> by <linux/of_clk.h>
  ARC: fpu: fix randconfig build error reported by 0-day test service
  ARC: fix some Kconfig typos
  ARC: Cleanup old Kconfig IO scheduler options
parents 6693075e 8d92e992
...@@ -154,7 +154,7 @@ config ARC_CPU_HS ...@@ -154,7 +154,7 @@ config ARC_CPU_HS
help help
Support for ARC HS38x Cores based on ARCv2 ISA Support for ARC HS38x Cores based on ARCv2 ISA
The notable features are: The notable features are:
- SMP configurations of upto 4 core with coherency - SMP configurations of up to 4 cores with coherency
- Optional L2 Cache and IO-Coherency - Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks, - Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore) auto stack switch, auto regfile save/restore)
...@@ -192,7 +192,7 @@ config ARC_SMP_HALT_ON_RESET ...@@ -192,7 +192,7 @@ config ARC_SMP_HALT_ON_RESET
help help
In SMP configuration cores can be configured as Halt-on-reset In SMP configuration cores can be configured as Halt-on-reset
or they could all start at same time. For Halt-on-reset, non or they could all start at same time. For Halt-on-reset, non
masters are parked until Master kicks them so they can start of masters are parked until Master kicks them so they can start off
at designated entry point. For other case, all jump to common at designated entry point. For other case, all jump to common
entry point and spin wait for Master's signal. entry point and spin wait for Master's signal.
......
...@@ -21,8 +21,6 @@ CONFIG_MODULES=y ...@@ -21,8 +21,6 @@ CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_EZNPS=y CONFIG_ARC_PLAT_EZNPS=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_NR_CPUS=4096 CONFIG_NR_CPUS=4096
......
...@@ -20,8 +20,6 @@ CONFIG_ISA_ARCOMPACT=y ...@@ -20,8 +20,6 @@ CONFIG_ISA_ARCOMPACT=y
CONFIG_KPROBES=y CONFIG_KPROBES=y
CONFIG_MODULES=y CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci" CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
# CONFIG_COMPACTION is not set # CONFIG_COMPACTION is not set
CONFIG_NET=y CONFIG_NET=y
......
...@@ -19,8 +19,6 @@ CONFIG_PERF_EVENTS=y ...@@ -19,8 +19,6 @@ CONFIG_PERF_EVENTS=y
CONFIG_KPROBES=y CONFIG_KPROBES=y
CONFIG_MODULES=y CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs" CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs"
# CONFIG_COMPACTION is not set # CONFIG_COMPACTION is not set
......
...@@ -14,8 +14,6 @@ CONFIG_PERF_EVENTS=y ...@@ -14,8 +14,6 @@ CONFIG_PERF_EVENTS=y
CONFIG_KPROBES=y CONFIG_KPROBES=y
CONFIG_MODULES=y CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_SMP=y CONFIG_SMP=y
# CONFIG_ARC_TIMERS_64BIT is not set # CONFIG_ARC_TIMERS_64BIT is not set
......
...@@ -43,6 +43,8 @@ extern void fpu_init_task(struct pt_regs *regs); ...@@ -43,6 +43,8 @@ extern void fpu_init_task(struct pt_regs *regs);
#endif /* !CONFIG_ISA_ARCOMPACT */ #endif /* !CONFIG_ISA_ARCOMPACT */
struct task_struct;
extern void fpu_save_restore(struct task_struct *p, struct task_struct *n); extern void fpu_save_restore(struct task_struct *p, struct task_struct *n);
#else /* !CONFIG_ARC_FPU_SAVE_RESTORE */ #else /* !CONFIG_ARC_FPU_SAVE_RESTORE */
......
...@@ -29,6 +29,8 @@ ...@@ -29,6 +29,8 @@
.endm .endm
#define ASM_NL ` /* use '`' to mark new line in macro */ #define ASM_NL ` /* use '`' to mark new line in macro */
#define __ALIGN .align 4
#define __ALIGN_STR __stringify(__ALIGN)
/* annotation for data we want in DCCM - if enabled in .config */ /* annotation for data we want in DCCM - if enabled in .config */
.macro ARCFP_DATA nm .macro ARCFP_DATA nm
......
...@@ -8,11 +8,11 @@ ...@@ -8,11 +8,11 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/root_dev.h> #include <linux/root_dev.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <linux/console.h> #include <linux/console.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/cpu.h> #include <linux/cpu.h>
#include <linux/of_clk.h>
#include <linux/of_fdt.h> #include <linux/of_fdt.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/cache.h> #include <linux/cache.h>
......
...@@ -104,8 +104,7 @@ static void show_faulting_vma(unsigned long address) ...@@ -104,8 +104,7 @@ static void show_faulting_vma(unsigned long address)
if (IS_ERR(nm)) if (IS_ERR(nm))
nm = "?"; nm = "?";
} }
pr_info(" @off 0x%lx in [%s]\n" pr_info(" @off 0x%lx in [%s] VMA: 0x%08lx to 0x%08lx\n",
" VMA: 0x%08lx to 0x%08lx\n",
vma->vm_start < TASK_UNMAPPED_BASE ? vma->vm_start < TASK_UNMAPPED_BASE ?
address : address - vma->vm_start, address : address - vma->vm_start,
nm, vma->vm_start, vma->vm_end); nm, vma->vm_start, vma->vm_end);
...@@ -120,8 +119,6 @@ static void show_ecr_verbose(struct pt_regs *regs) ...@@ -120,8 +119,6 @@ static void show_ecr_verbose(struct pt_regs *regs)
unsigned int vec, cause_code; unsigned int vec, cause_code;
unsigned long address; unsigned long address;
pr_info("\n[ECR ]: 0x%08lx => ", regs->event);
/* For Data fault, this is data address not instruction addr */ /* For Data fault, this is data address not instruction addr */
address = current->thread.fault_address; address = current->thread.fault_address;
...@@ -130,10 +127,10 @@ static void show_ecr_verbose(struct pt_regs *regs) ...@@ -130,10 +127,10 @@ static void show_ecr_verbose(struct pt_regs *regs)
/* For DTLB Miss or ProtV, display the memory involved too */ /* For DTLB Miss or ProtV, display the memory involved too */
if (vec == ECR_V_DTLB_MISS) { if (vec == ECR_V_DTLB_MISS) {
pr_cont("Invalid %s @ 0x%08lx by insn @ 0x%08lx\n", pr_cont("Invalid %s @ 0x%08lx by insn @ %pS\n",
(cause_code == 0x01) ? "Read" : (cause_code == 0x01) ? "Read" :
((cause_code == 0x02) ? "Write" : "EX"), ((cause_code == 0x02) ? "Write" : "EX"),
address, regs->ret); address, (void *)regs->ret);
} else if (vec == ECR_V_ITLB_MISS) { } else if (vec == ECR_V_ITLB_MISS) {
pr_cont("Insn could not be fetched\n"); pr_cont("Insn could not be fetched\n");
} else if (vec == ECR_V_MACH_CHK) { } else if (vec == ECR_V_MACH_CHK) {
...@@ -191,31 +188,31 @@ void show_regs(struct pt_regs *regs) ...@@ -191,31 +188,31 @@ void show_regs(struct pt_regs *regs)
show_ecr_verbose(regs); show_ecr_verbose(regs);
pr_info("[EFA ]: 0x%08lx\n[BLINK ]: %pS\n[ERET ]: %pS\n",
current->thread.fault_address,
(void *)regs->blink, (void *)regs->ret);
if (user_mode(regs)) if (user_mode(regs))
show_faulting_vma(regs->ret); /* faulting code, not data */ show_faulting_vma(regs->ret); /* faulting code, not data */
pr_info("[STAT32]: 0x%08lx", regs->status32); pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\n",
regs->event, current->thread.fault_address, regs->ret);
pr_info("STAT32: 0x%08lx", regs->status32);
#define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : "" #define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : ""
#ifdef CONFIG_ISA_ARCOMPACT #ifdef CONFIG_ISA_ARCOMPACT
pr_cont(" : %2s%2s%2s%2s%2s%2s%2s\n", pr_cont(" [%2s%2s%2s%2s%2s%2s%2s]",
(regs->status32 & STATUS_U_MASK) ? "U " : "K ", (regs->status32 & STATUS_U_MASK) ? "U " : "K ",
STS_BIT(regs, DE), STS_BIT(regs, AE), STS_BIT(regs, DE), STS_BIT(regs, AE),
STS_BIT(regs, A2), STS_BIT(regs, A1), STS_BIT(regs, A2), STS_BIT(regs, A1),
STS_BIT(regs, E2), STS_BIT(regs, E1)); STS_BIT(regs, E2), STS_BIT(regs, E1));
#else #else
pr_cont(" : %2s%2s%2s%2s\n", pr_cont(" [%2s%2s%2s%2s]",
STS_BIT(regs, IE), STS_BIT(regs, IE),
(regs->status32 & STATUS_U_MASK) ? "U " : "K ", (regs->status32 & STATUS_U_MASK) ? "U " : "K ",
STS_BIT(regs, DE), STS_BIT(regs, AE)); STS_BIT(regs, DE), STS_BIT(regs, AE));
#endif #endif
pr_info("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", pr_cont(" BTA: 0x%08lx\n", regs->bta);
regs->bta, regs->sp, regs->fp); pr_info("BLK: %pS\n SP: 0x%08lx FP: 0x%08lx\n",
(void *)regs->blink, regs->sp, regs->fp);
pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
regs->lp_start, regs->lp_end, regs->lp_count); regs->lp_start, regs->lp_end, regs->lp_count);
......
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