Commit 318f89ca authored by Tvrtko Ursulin's avatar Tvrtko Ursulin

drm/i915: Initialize legacy semaphores from engine hw id indexed array

Build the legacy semaphore initialisation array using the engine
hardware ids instead of driver internal ones. This makes the
static array size dependent only on the number of gen6 semaphore
engines.

Also makes the per-engine semaphore wait and signal tables
hardware id indexed saving some more space.

v2: Refactor I915_GEN6_NUM_ENGINES to GEN6_SEMAPHORE_LAST. (Chris Wilson)
v3: More polish. (Chris Wilson)
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1471363461-9973-1-git-send-email-tvrtko.ursulin@linux.intel.com
parent 5ec2cf7e
...@@ -1337,8 +1337,7 @@ static int gen6_signal(struct drm_i915_gem_request *req) ...@@ -1337,8 +1337,7 @@ static int gen6_signal(struct drm_i915_gem_request *req)
{ {
struct intel_ring *ring = req->ring; struct intel_ring *ring = req->ring;
struct drm_i915_private *dev_priv = req->i915; struct drm_i915_private *dev_priv = req->i915;
struct intel_engine_cs *useless; struct intel_engine_cs *engine;
enum intel_engine_id id;
int ret, num_rings; int ret, num_rings;
num_rings = INTEL_INFO(dev_priv)->num_rings; num_rings = INTEL_INFO(dev_priv)->num_rings;
...@@ -1346,9 +1345,13 @@ static int gen6_signal(struct drm_i915_gem_request *req) ...@@ -1346,9 +1345,13 @@ static int gen6_signal(struct drm_i915_gem_request *req)
if (ret) if (ret)
return ret; return ret;
for_each_engine_id(useless, dev_priv, id) { for_each_engine(engine, dev_priv) {
i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; i915_reg_t mbox_reg;
if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
continue;
mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id];
if (i915_mmio_reg_valid(mbox_reg)) { if (i915_mmio_reg_valid(mbox_reg)) {
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit_reg(ring, mbox_reg); intel_ring_emit_reg(ring, mbox_reg);
...@@ -1495,7 +1498,7 @@ gen6_ring_sync_to(struct drm_i915_gem_request *req, ...@@ -1495,7 +1498,7 @@ gen6_ring_sync_to(struct drm_i915_gem_request *req,
u32 dw1 = MI_SEMAPHORE_MBOX | u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER; MI_SEMAPHORE_REGISTER;
u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id]; u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id];
int ret; int ret;
WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
...@@ -2569,41 +2572,41 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, ...@@ -2569,41 +2572,41 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
* initialized as INVALID. Gen8 will initialize the * initialized as INVALID. Gen8 will initialize the
* sema between VCS2 and RCS later. * sema between VCS2 and RCS later.
*/ */
for (i = 0; i < I915_NUM_ENGINES; i++) { for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
static const struct { static const struct {
u32 wait_mbox; u32 wait_mbox;
i915_reg_t mbox_reg; i915_reg_t mbox_reg;
} sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
[RCS] = { [RCS_HW] = {
[VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC },
[BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC },
[VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
}, },
[VCS] = { [VCS_HW] = {
[RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC },
[BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC },
[VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
}, },
[BCS] = { [BCS_HW] = {
[RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC },
[VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC },
[VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
}, },
[VECS] = { [VECS_HW] = {
[RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
[VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
[BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
}, },
}; };
u32 wait_mbox; u32 wait_mbox;
i915_reg_t mbox_reg; i915_reg_t mbox_reg;
if (i == engine->id || i == VCS2) { if (i == engine->hw_id) {
wait_mbox = MI_SEMAPHORE_SYNC_INVALID; wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
mbox_reg = GEN6_NOSYNC; mbox_reg = GEN6_NOSYNC;
} else { } else {
wait_mbox = sem_data[engine->id][i].wait_mbox; wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
mbox_reg = sem_data[engine->id][i].mbox_reg; mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
} }
engine->semaphore.mbox.wait[i] = wait_mbox; engine->semaphore.mbox.wait[i] = wait_mbox;
......
...@@ -278,11 +278,14 @@ struct intel_engine_cs { ...@@ -278,11 +278,14 @@ struct intel_engine_cs {
u32 sync_seqno[I915_NUM_ENGINES-1]; u32 sync_seqno[I915_NUM_ENGINES-1];
union { union {
#define GEN6_SEMAPHORE_LAST VECS_HW
#define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
#define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
struct { struct {
/* our mbox written by others */ /* our mbox written by others */
u32 wait[I915_NUM_ENGINES]; u32 wait[GEN6_NUM_SEMAPHORES];
/* mboxes this ring signals to */ /* mboxes this ring signals to */
i915_reg_t signal[I915_NUM_ENGINES]; i915_reg_t signal[GEN6_NUM_SEMAPHORES];
} mbox; } mbox;
u64 signal_ggtt[I915_NUM_ENGINES]; u64 signal_ggtt[I915_NUM_ENGINES];
}; };
......
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