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nexedi
linux
Commits
31c8ebee
Commit
31c8ebee
authored
Jan 10, 2003
by
Paul Mackerras
Browse files
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Plain Diff
PPC32: Add support for the IBM PPC 405GPR-based "Sycamore" board.
parent
28f15a4c
Changes
6
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6 changed files
with
1454 additions
and
3 deletions
+1454
-3
arch/ppc/configs/redwood6_defconfig
arch/ppc/configs/redwood6_defconfig
+547
-0
arch/ppc/configs/sycamore_defconfig
arch/ppc/configs/sycamore_defconfig
+528
-0
arch/ppc/platforms/4xx/Kconfig
arch/ppc/platforms/4xx/Kconfig
+14
-3
arch/ppc/platforms/4xx/Makefile
arch/ppc/platforms/4xx/Makefile
+1
-0
arch/ppc/platforms/4xx/sycamore.c
arch/ppc/platforms/4xx/sycamore.c
+293
-0
arch/ppc/platforms/4xx/sycamore.h
arch/ppc/platforms/4xx/sycamore.h
+71
-0
No files found.
arch/ppc/configs/redwood6_defconfig
0 → 100644
View file @
31c8ebee
This diff is collapsed.
Click to expand it.
arch/ppc/configs/sycamore_defconfig
0 → 100644
View file @
31c8ebee
This diff is collapsed.
Click to expand it.
arch/ppc/platforms/4xx/Kconfig
View file @
31c8ebee
...
...
@@ -44,6 +44,9 @@ config REDWOOD_5
config REDWOOD_6
bool "Redwood-6"
config SYCAMORE
bool "Sycamore"
config TIVO
bool "Tivo"
...
...
@@ -81,7 +84,7 @@ config IBM405_ERR51
config IBM_OCP
bool
depends on ASH || BEECH || CEDAR || CPCI405 || EP405 || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 || WALNUT
depends on ASH || BEECH || CEDAR || CPCI405 || EP405 || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 ||
SYCAMORE ||
WALNUT
default y
config NP405L
...
...
@@ -91,7 +94,7 @@ config NP405L
config BIOS_FIXUP
bool
depends on CEDAR || EP405 || WALNUT
depends on CEDAR || EP405 ||
SYCAMORE ||
WALNUT
default y
config 403GCX
...
...
@@ -104,6 +107,14 @@ config 405GP
depends on CPCI405 || EP405 || WALNUT
default y
config 405GPR
bool
depends on SYCAMORE
config 405LP
bool
depends on CEDAR
config STB03xxx
bool
depends on REDWOOD_5 || REDWOOD_4 || REDWOOD_6
...
...
@@ -116,7 +127,7 @@ config EMBEDDEDBOOT
config IBM_OPENBIOS
bool
depends on ASH || BEECH || CEDAR || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 || WALNUT
depends on ASH || BEECH || CEDAR || REDWOOD_4 || REDWOOD_5 || REDWOOD_6 ||
SYCAMORE ||
WALNUT
default y
config 405_DMA
...
...
arch/ppc/platforms/4xx/Makefile
View file @
31c8ebee
...
...
@@ -12,6 +12,7 @@ obj-$(CONFIG_OAK) += oak.o
obj-$(CONFIG_REDWOOD_4)
+=
redwood.o
obj-$(CONFIG_REDWOOD_5)
+=
redwood5.o
obj-$(CONFIG_REDWOOD_6)
+=
redwood6.o
obj-$(CONFIG_SYCAMORE)
+=
sycamore.o
obj-$(CONFIG_WALNUT)
+=
walnut.o
obj-$(CONFIG_NP405L)
+=
ibmnp405l.o
...
...
arch/ppc/platforms/4xx/sycamore.c
0 → 100644
View file @
31c8ebee
/*
*
* Copyright 2000-2002 MontaVista Software Inc.
* Author: Armin Kuster <akuster@mvista.com>
* MontaVista Software, Inc. <source@mvista.com>
*
* Module name: sycamore.c
*
* Description:
* Architecture- / platform-specific boot-time initialization code for
* IBM PowerPC 4xx based boards.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/blk.h>
#include <linux/pci.h>
#include <linux/rtc.h>
#include <asm/ocp.h>
#include <asm/ppc4xx_pic.h>
#include <asm/system.h>
#include <asm/pci-bridge.h>
#include <asm/processor.h>
#include <asm/machdep.h>
#include <asm/page.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/todc.h>
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
void
*
kb_cs
;
void
*
kb_data
;
void
*
sycamore_rtc_base
;
/*
* Define all of the IRQ senses and polarities.
*/
static
u_char
Sycamore_IRQ_initsenses
[]
__initdata
=
{
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 0: Uart 0*/
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 1: Uart 1*/
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 2: IIC */
(
IRQ_SENSE_EDGE
|
IRQ_POLARITY_POSITIVE
),
/* 3: External Master */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 4: PCI ext cmd write*/
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 5: DMA Chan 0 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 6: DMA Chan 1 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 7: DMA Chan 2 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 8: DMA Chan 3 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 9: Ethernet wakeup (WOL)*/
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 10: Mal (SEER) */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 11: Mal TXEOB */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 12: Mal RXEOB */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 13: Mal TXDE*/
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 14: Mal RXDE*/
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 15: Ethernet */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 16: Ext PCI SERR */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 17: ECC */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_POSITIVE
),
/* 18: PCI PM*/
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 19: Ext Int 7 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 20: Ext Int 8 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 21: Ext Int 9 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 22: Ext Int 10 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 23: Ext Int 11 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 24: Ext Int 12 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 25: Ext Int 0 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 26: Ext Int 1 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 27: Ext Int 2 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 28: Ext Int 3 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 29: Ext Int 4 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 30: Ext Int 5 */
(
IRQ_SENSE_LEVEL
|
IRQ_POLARITY_NEGATIVE
),
/* 31: Ext Int 6 */
};
/* Some IRQs unique to Sycamore.
* Used by the generic 405 PCI setup functions in ppc4xx_pci.c
*/
int
__init
ppc405_map_irq
(
struct
pci_dev
*
dev
,
unsigned
char
idsel
,
unsigned
char
pin
)
{
static
char
pci_irq_table
[][
4
]
=
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{
28
,
28
,
28
,
28
},
/* IDSEL 1 - PCI slot 1 */
{
29
,
29
,
29
,
29
},
/* IDSEL 2 - PCI slot 2 */
{
30
,
30
,
30
,
30
},
/* IDSEL 3 - PCI slot 3 */
{
31
,
31
,
31
,
31
},
/* IDSEL 4 - PCI slot 4 */
};
const
long
min_idsel
=
1
,
max_idsel
=
4
,
irqs_per_slot
=
4
;
return
PCI_IRQ_TABLE_LOOKUP
;
};
void
__init
sycamore_setup_arch
(
void
)
{
#define SYCAMORE_PS2_BASE 0xF0100000
#define SYCAMORE_FPGA_BASE 0xF0300000
void
*
fpga_brdc
;
unsigned
char
fpga_brdc_data
;
void
*
fpga_enable
;
void
*
fpga_polarity
;
void
*
fpga_status
;
void
*
fpga_trigger
;
ppc4xx_setup_arch
();
kb_data
=
ioremap
(
SYCAMORE_PS2_BASE
,
8
);
if
(
!
kb_data
)
{
printk
(
KERN_CRIT
"sycamore_setup_arch() kb_data ioremap failed
\n
"
);
return
;
}
kb_cs
=
kb_data
+
1
;
fpga_status
=
ioremap
(
SYCAMORE_FPGA_BASE
,
8
);
if
(
!
fpga_status
)
{
printk
(
KERN_CRIT
"sycamore_setup_arch() fpga_status ioremap failed
\n
"
);
return
;
}
fpga_enable
=
fpga_status
+
1
;
fpga_polarity
=
fpga_status
+
2
;
fpga_trigger
=
fpga_status
+
3
;
fpga_brdc
=
fpga_status
+
4
;
/* split the keyboard and mouse interrupts */
fpga_brdc_data
=
readb
(
fpga_brdc
);
fpga_brdc_data
|=
0x80
;
writeb
(
fpga_brdc_data
,
fpga_brdc
);
writeb
(
0x3
,
fpga_enable
);
writeb
(
0x3
,
fpga_polarity
);
writeb
(
0x3
,
fpga_trigger
);
/* RTC step for the sycamore */
sycamore_rtc_base
=
(
void
*
)
SYCAMORE_RTC_VADDR
;
TODC_INIT
(
TODC_TYPE_DS1743
,
sycamore_rtc_base
,
sycamore_rtc_base
,
sycamore_rtc_base
,
8
);
ibm4xxPIC_InitSenses
=
Sycamore_IRQ_initsenses
;
ibm4xxPIC_NumInitSenses
=
sizeof
(
Sycamore_IRQ_initsenses
);
/* Identify the system */
printk
(
KERN_INFO
"IBM Sycamore (IBM405GPr) Platform
\n
"
);
printk
(
KERN_INFO
"Port by MontaVista Software, Inc. (source@mvista.com)
\n
"
);
}
void
__init
bios_fixup
(
struct
pci_controller
*
hose
,
struct
pcil0_regs
*
pcip
)
{
#ifdef CONFIG_PCI
unsigned
int
bar_response
,
bar
;
/*
* Expected PCI mapping:
*
* PLB addr PCI memory addr
* --------------------- ---------------------
* 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
* 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
*
* PLB addr PCI io addr
* --------------------- ---------------------
* e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
*
* The following code is simplified by assuming that the bootrom
* has been well behaved in following this mapping.
*/
#ifdef DEBUG
int
i
;
printk
(
"ioremap PCLIO_BASE = 0x%x
\n
"
,
pcip
);
printk
(
"PCI bridge regs before fixup
\n
"
);
for
(
i
=
0
;
i
<=
3
;
i
++
)
{
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
ma
)));
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
la
)));
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
pcila
)));
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
pciha
)));
}
printk
(
" ptm1ms
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm1ms
)));
printk
(
" ptm1la
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm1la
)));
printk
(
" ptm2ms
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm2ms
)));
printk
(
" ptm2la
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm2la
)));
#endif
/* added for IBM boot rom version 1.15 bios bar changes -AK */
/* Disable region first */
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
0
].
ma
),
0x00000000
);
/* PLB starting addr, PCI: 0x80000000 */
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
0
].
la
),
0x80000000
);
/* PCI start addr, 0x80000000 */
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
0
].
pcila
),
PPC405_PCI_MEM_BASE
);
/* 512MB range of PLB to PCI */
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
0
].
pciha
),
0x00000000
);
/* Enable no pre-fetch, enable region */
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
0
].
ma
),
((
0xffffffff
-
(
PPC405_PCI_UPPER_MEM
-
PPC405_PCI_MEM_BASE
))
|
0x01
));
/* Disable region one */
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
1
].
ma
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
1
].
la
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
1
].
pcila
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
1
].
pciha
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
1
].
ma
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
ptm1ms
),
0x00000000
);
/* Disable region two */
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
2
].
ma
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
2
].
la
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
2
].
pcila
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
2
].
pciha
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
pmm
[
2
].
ma
),
0x00000000
);
out_le32
((
void
*
)
&
(
pcip
->
ptm2ms
),
0x00000000
);
/* Zero config bars */
for
(
bar
=
PCI_BASE_ADDRESS_1
;
bar
<=
PCI_BASE_ADDRESS_2
;
bar
+=
4
)
{
early_write_config_dword
(
hose
,
hose
->
first_busno
,
PCI_FUNC
(
hose
->
first_busno
),
bar
,
0x00000000
);
early_read_config_dword
(
hose
,
hose
->
first_busno
,
PCI_FUNC
(
hose
->
first_busno
),
bar
,
&
bar_response
);
DBG
(
"BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x
\n
"
,
hose
->
first_busno
,
PCI_SLOT
(
hose
->
first_busno
),
PCI_FUNC
(
hose
->
first_busno
),
bar
,
bar_response
);
}
/* end work arround */
#ifdef DEBUG
printk
(
"PCI bridge regs after fixup
\n
"
);
for
(
i
=
0
;
i
<=
3
;
i
++
)
{
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
ma
)));
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
la
)));
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
pcila
)));
printk
(
" pmm%dma
\t
0x%x
\n
"
,
i
,
in_le32
(
&
(
pcip
->
pmm
[
i
].
pciha
)));
}
printk
(
" ptm1ms
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm1ms
)));
printk
(
" ptm1la
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm1la
)));
printk
(
" ptm2ms
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm2ms
)));
printk
(
" ptm2la
\t
0x%x
\n
"
,
in_le32
(
&
(
pcip
->
ptm2la
)));
#endif
#endif
}
void
__init
sycamore_map_io
(
void
)
{
ppc4xx_map_io
();
io_block_mapping
(
SYCAMORE_RTC_VADDR
,
SYCAMORE_RTC_PADDR
,
SYCAMORE_RTC_SIZE
,
_PAGE_IO
);
}
void
__init
platform_init
(
unsigned
long
r3
,
unsigned
long
r4
,
unsigned
long
r5
,
unsigned
long
r6
,
unsigned
long
r7
)
{
ppc4xx_init
(
r3
,
r4
,
r5
,
r6
,
r7
);
ppc_md
.
setup_arch
=
sycamore_setup_arch
;
ppc_md
.
setup_io_mappings
=
sycamore_map_io
;
ppc_md
.
time_init
=
todc_time_init
;
ppc_md
.
set_rtc_time
=
todc_set_rtc_time
;
ppc_md
.
get_rtc_time
=
todc_get_rtc_time
;
ppc_md
.
nvram_read_val
=
todc_direct_read_val
;
ppc_md
.
nvram_write_val
=
todc_direct_write_val
;
}
arch/ppc/platforms/4xx/sycamore.h
0 → 100755
View file @
31c8ebee
/*
*
* Copyright 2000 MontaVista Software Inc.
* Author: Armin Kuster <akuster@mvista.com>
* MontaVista Software, Inc.
*
* Module name: sycamore.h
*
* Description:
* Macros, definitions, and data structures specific to the IBM PowerPC
* based boards.
*
* This includes:
*
* 405GP "Sycamore" evaluation board
*
*/
#ifdef __KERNEL__
#ifndef __ASM_SYCAMORE_H__
#define __ASM_SYCAMORE_H__
#include <platforms/4xx/ibm405gpr.h>
#ifndef __ASSEMBLY__
/*
* Data structure defining board information maintained by the boot
* ROM on IBM's "Sycamore" evaluation board. An effort has been made to
* keep the field names consistent with the 8xx 'bd_t' board info
* structures.
*/
typedef
struct
board_info
{
unsigned
char
bi_s_version
[
4
];
/* Version of this structure */
unsigned
char
bi_r_version
[
30
];
/* Version of the IBM ROM */
unsigned
int
bi_memsize
;
/* DRAM installed, in bytes */
unsigned
char
bi_enetaddr
[
6
];
/* Local Ethernet MAC address */
unsigned
char
bi_pci_enetaddr
[
6
];
/* PCI Ethernet MAC address */
unsigned
int
bi_intfreq
;
/* Processor speed, in Hz */
unsigned
int
bi_busfreq
;
/* PLB Bus speed, in Hz */
unsigned
int
bi_pci_busfreq
;
/* PCI Bus speed, in Hz */
}
bd_t
;
/* Some 4xx parts use a different timebase frequency from the internal clock.
*/
#define bi_tbfreq bi_intfreq
/* Memory map for the IBM "Sycamore" 405GP evaluation board.
* Generic 4xx plus RTC.
*/
extern
void
*
sycamore_rtc_base
;
#define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
#define SYCAMORE_RTC_SIZE ((uint)8*1024)
#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
#define BASE_BAUD 201600
#else
#define BASE_BAUD 691200
#endif
#define SYCAMORE_PS2_BASE 0xF0100000
#define SYCAMORE_FPGA_BASE 0xF0300000
#define PPC4xx_MACHINE_NAME "IBM Sycamore"
#endif
/* !__ASSEMBLY__ */
#endif
/* __ASM_SYCAMORE_H__ */
#endif
/* __KERNEL__ */
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