Commit 350ab42f authored by Imre Deak's avatar Imre Deak

drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation

Split out the PLL parameter->frequency conversion logic for each type of
PLL for symmetry with their corresponding inverse conversion functions.
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-11-imre.deak@intel.com
parent 068f723e
...@@ -877,9 +877,11 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, ...@@ -877,9 +877,11 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
return pll; return pll;
} }
static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
i915_reg_t reg) const struct intel_shared_dpll *pll)
{ {
i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ?
WRPLL_CTL(0) : WRPLL_CTL(1);
int refclk; int refclk;
int n, p, r; int n, p, r;
u32 wrpll; u32 wrpll;
...@@ -921,7 +923,7 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, ...@@ -921,7 +923,7 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
/* Convert to KHz, p & r have a fixed point portion */ /* Convert to KHz, p & r have a fixed point portion */
return (refclk * n * 100) / (p * r); return (refclk * n * 100) / (p * r) * 2;
} }
static struct intel_shared_dpll * static struct intel_shared_dpll *
...@@ -956,6 +958,29 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) ...@@ -956,6 +958,29 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll; return pll;
} }
static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll)
{
int link_clock = 0;
switch (pll->info->id) {
case DPLL_ID_LCPLL_810:
link_clock = 81000;
break;
case DPLL_ID_LCPLL_1350:
link_clock = 135000;
break;
case DPLL_ID_LCPLL_2700:
link_clock = 270000;
break;
default:
drm_WARN(&i915->drm, 1, "bad port clock sel\n");
break;
}
return link_clock * 2;
}
static struct intel_shared_dpll * static struct intel_shared_dpll *
hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc) struct intel_crtc *crtc)
...@@ -973,6 +998,29 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, ...@@ -973,6 +998,29 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SPLL)); BIT(DPLL_ID_SPLL));
} }
static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll)
{
int link_clock = 0;
switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) {
case SPLL_FREQ_810MHz:
link_clock = 81000;
break;
case SPLL_FREQ_1350MHz:
link_clock = 135000;
break;
case SPLL_FREQ_2700MHz:
link_clock = 270000;
break;
default:
drm_WARN(&i915->drm, 1, "bad spll freq\n");
break;
}
return link_clock * 2;
}
static bool hsw_get_dpll(struct intel_atomic_state *state, static bool hsw_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc, struct intel_crtc *crtc,
struct intel_encoder *encoder) struct intel_encoder *encoder)
...@@ -1008,44 +1056,17 @@ static int hsw_ddi_clock_get(struct intel_encoder *encoder, ...@@ -1008,44 +1056,17 @@ static int hsw_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config) struct intel_crtc_state *pipe_config)
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int link_clock = 0; struct intel_shared_dpll *pll = pipe_config->shared_dpll;
u32 pll;
switch (pipe_config->shared_dpll->info->id) { switch (pll->info->id) {
case DPLL_ID_LCPLL_810:
link_clock = 81000;
break;
case DPLL_ID_LCPLL_1350:
link_clock = 135000;
break;
case DPLL_ID_LCPLL_2700:
link_clock = 270000;
break;
case DPLL_ID_WRPLL1: case DPLL_ID_WRPLL1:
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
break;
case DPLL_ID_WRPLL2: case DPLL_ID_WRPLL2:
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); return hsw_ddi_wrpll_get_freq(dev_priv, pll);
break;
case DPLL_ID_SPLL: case DPLL_ID_SPLL:
pll = intel_de_read(dev_priv, SPLL_CTL) & SPLL_FREQ_MASK; return hsw_ddi_spll_get_freq(dev_priv, pll);
if (pll == SPLL_FREQ_810MHz)
link_clock = 81000;
else if (pll == SPLL_FREQ_1350MHz)
link_clock = 135000;
else if (pll == SPLL_FREQ_2700MHz)
link_clock = 270000;
else {
drm_WARN(&dev_priv->drm, 1, "bad spll freq\n");
break;
}
break;
default: default:
drm_WARN(&dev_priv->drm, 1, "bad port clock sel\n"); return hsw_ddi_lcpll_get_freq(dev_priv, pll);
break;
} }
return link_clock * 2;
} }
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
......
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