Commit 35832e26 authored by Marc St-Jean's avatar Marc St-Jean Committed by Ralf Baechle

[MIPS] PMC MSP71xx core platform

Patch to add core platform support for the PMC-Sierra MSP71xx devices.
Signed-off-by: default avatarMarc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a4b156d4
#
# Makefile for the PMC-Sierra MSP SOCs
#
obj-y += msp_prom.o msp_setup.o msp_irq.o \
msp_time.o msp_serial.o msp_elb.o
obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
obj-$(CONFIG_PCI) += msp_pci.o
obj-$(CONFIG_MSPETH) += msp_eth.o
obj-$(CONFIG_USB_MSP71XX) += msp_usb.o
/*
* Sets up the proper Chip Select configuration registers. It is assumed that
* PMON sets up the ADDR and MASK registers properly.
*
* Copyright 2005-2006 PMC-Sierra, Inc.
* Author: Marc St-Jean, Marc_St-Jean@pmc-sierra.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <msp_regs.h>
static int __init msp_elb_setup(void)
{
#if defined(CONFIG_PMC_MSP7120_GW) \
|| defined(CONFIG_PMC_MSP7120_EVAL)
/*
* Force all CNFG to be identical and equal to CS0,
* according to OPS doc
*/
*CS1_CNFG_REG = *CS2_CNFG_REG = *CS3_CNFG_REG = *CS0_CNFG_REG;
#endif
return 0;
}
subsys_initcall(msp_elb_setup);
/*
* Sets up interrupt handlers for various hardware switches which are
* connected to interrupt lines.
*
* Copyright 2005-2207 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <msp_int.h>
#include <msp_regs.h>
#include <msp_regops.h>
#ifdef CONFIG_PMCTWILED
#include <msp_led_macros.h>
#endif
/* For hwbutton_interrupt->initial_state */
#define HWBUTTON_HI 0x1
#define HWBUTTON_LO 0x2
/*
* This struct describes a hardware button
*/
struct hwbutton_interrupt {
char *name; /* Name of button */
int irq; /* Actual LINUX IRQ */
int eirq; /* Extended IRQ number (0-7) */
int initial_state; /* The "normal" state of the switch */
void (*handle_hi)(void *); /* Handler: switch input has gone HI */
void (*handle_lo)(void *); /* Handler: switch input has gone LO */
void *data; /* Optional data to pass to handler */
};
#ifdef CONFIG_PMC_MSP7120_GW
extern void msp_restart(char *);
static void softreset_push(void *data)
{
printk(KERN_WARNING "SOFTRESET switch was pushed\n");
/*
* In the future you could move this to the release handler,
* timing the difference between the 'push' and 'release', and only
* doing this ungraceful restart if the button has been down for
* a certain amount of time; otherwise doing a graceful restart.
*/
msp_restart(NULL);
}
static void softreset_release(void *data)
{
printk(KERN_WARNING "SOFTRESET switch was released\n");
/* Do nothing */
}
static void standby_on(void *data)
{
printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n");
/* TODO: Put board in standby mode */
#ifdef CONFIG_PMCTWILED
msp_led_turn_off(MSP_LED_PWRSTANDBY_GREEN);
msp_led_turn_on(MSP_LED_PWRSTANDBY_RED);
#endif
}
static void standby_off(void *data)
{
printk(KERN_WARNING
"STANDBY switch was set to OFF (not implemented)\n");
/* TODO: Take out of standby mode */
#ifdef CONFIG_PMCTWILED
msp_led_turn_on(MSP_LED_PWRSTANDBY_GREEN);
msp_led_turn_off(MSP_LED_PWRSTANDBY_RED);
#endif
}
static struct hwbutton_interrupt softreset_sw = {
.name = "Softreset button",
.irq = MSP_INT_EXT0,
.eirq = 0,
.initial_state = HWBUTTON_HI,
.handle_hi = softreset_release,
.handle_lo = softreset_push,
.data = NULL,
};
static struct hwbutton_interrupt standby_sw = {
.name = "Standby switch",
.irq = MSP_INT_EXT1,
.eirq = 1,
.initial_state = HWBUTTON_HI,
.handle_hi = standby_off,
.handle_lo = standby_on,
.data = NULL,
};
#endif /* CONFIG_PMC_MSP7120_GW */
static irqreturn_t hwbutton_handler(int irq, void *data)
{
struct hwbutton_interrupt *hirq = data;
unsigned long cic_ext = *CIC_EXT_CFG_REG;
if (irq != hirq->irq)
return IRQ_NONE;
if (CIC_EXT_IS_ACTIVE_HI(cic_ext, hirq->eirq)) {
/* Interrupt: pin is now HI */
CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
hirq->handle_hi(hirq->data);
} else {
/* Interrupt: pin is now LO */
CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
hirq->handle_lo(hirq->data);
}
/*
* Invert the POLARITY of this level interrupt to ack the interrupt
* Thus next state change will invoke the opposite message
*/
*CIC_EXT_CFG_REG = cic_ext;
return IRQ_HANDLED;
}
static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
{
unsigned long cic_ext;
if (hirq->handle_hi == NULL || hirq->handle_lo == NULL)
return -EINVAL;
cic_ext = *CIC_EXT_CFG_REG;
CIC_EXT_SET_TRIGGER_LEVEL(cic_ext, hirq->eirq);
if (hirq->initial_state == HWBUTTON_HI)
CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
else
CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
*CIC_EXT_CFG_REG = cic_ext;
return request_irq(hirq->irq, hwbutton_handler, SA_INTERRUPT,
hirq->name, (void *)hirq);
}
static int __init msp_hwbutton_setup(void)
{
#ifdef CONFIG_PMC_MSP7120_GW
msp_hwbutton_register(&softreset_sw);
msp_hwbutton_register(&standby_sw);
#endif
return 0;
}
subsys_initcall(msp_hwbutton_setup);
/*
* IRQ vector handles
*
* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/time.h>
#include <asm/irq_cpu.h>
#include <msp_int.h>
extern void msp_int_handle(void);
/* SLP bases systems */
extern void msp_slp_irq_init(void);
extern void msp_slp_irq_dispatch(void);
/* CIC based systems */
extern void msp_cic_irq_init(void);
extern void msp_cic_irq_dispatch(void);
/*
* The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
* hierarchical system. The first level are the direct MIPS interrupts
* and are assigned the interrupt range 0-7. The second level is the SLM
* interrupt controller and is assigned the range 8-39. The third level
* comprises the Peripherial block, the PCI block, the PCI MSI block and
* the SLP. The PCI interrupts and the SLP errors are handled by the
* relevant subsystems so the core interrupt code needs only concern
* itself with the Peripheral block. These are assigned interrupts in
* the range 40-71.
*/
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
u32 pending;
pending = read_c0_status() & read_c0_cause();
/*
* jump to the correct interrupt routine
* These are arranged in priority order and the timer
* comes first!
*/
#ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */
if (pending & C_IRQ4) /* do the peripherals first, that's the timer */
msp_cic_irq_dispatch();
else if (pending & C_IRQ0)
do_IRQ(MSP_INT_MAC0);
else if (pending & C_IRQ1)
do_IRQ(MSP_INT_MAC1);
else if (pending & C_IRQ2)
do_IRQ(MSP_INT_USB);
else if (pending & C_IRQ3)
do_IRQ(MSP_INT_SAR);
else if (pending & C_IRQ5)
do_IRQ(MSP_INT_SEC);
#else
if (pending & C_IRQ5)
do_IRQ(MSP_INT_TIMER);
else if (pending & C_IRQ0)
do_IRQ(MSP_INT_MAC0);
else if (pending & C_IRQ1)
do_IRQ(MSP_INT_MAC1);
else if (pending & C_IRQ3)
do_IRQ(MSP_INT_VE);
else if (pending & C_IRQ4)
msp_slp_irq_dispatch();
#endif
else if (pending & C_SW0) /* do software after hardware */
do_IRQ(MSP_INT_SW0);
else if (pending & C_SW1)
do_IRQ(MSP_INT_SW1);
}
static struct irqaction cascade_msp = {
.handler = no_action,
.name = "MSP cascade"
};
void __init arch_init_irq(void)
{
/* initialize the 1st-level CPU based interrupt controller */
mips_cpu_irq_init();
#ifdef CONFIG_IRQ_MSP_CIC
msp_cic_irq_init();
/* setup the cascaded interrupts */
setup_irq(MSP_INT_CIC, &cascade_msp);
setup_irq(MSP_INT_PER, &cascade_msp);
#else
/* setup the 2nd-level SLP register based interrupt controller */
msp_slp_irq_init();
/* setup the cascaded SLP/PER interrupts */
setup_irq(MSP_INT_SLP, &cascade_msp);
setup_irq(MSP_INT_PER, &cascade_msp);
#endif
}
/*
* This file define the irq handler for MSP SLM subsystem interrupts.
*
* Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <msp_cic_int.h>
#include <msp_regs.h>
/*
* NOTE: We are only enabling support for VPE0 right now.
*/
static inline void unmask_msp_cic_irq(unsigned int irq)
{
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE));
else
*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
}
static inline void mask_msp_cic_irq(unsigned int irq)
{
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE));
else
*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
}
/*
* While we ack the interrupt interrupts are disabled and thus we don't need
* to deal with concurrency issues. Same for msp_cic_irq_end.
*/
static inline void ack_msp_cic_irq(unsigned int irq)
{
mask_msp_cic_irq(irq);
/*
* only really necessary for 18, 16-14 and sometimes 3:0 (since
* these can be edge sensitive) but it doesn't hurt for the others.
*/
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE));
else
*PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
}
static struct irq_chip msp_cic_irq_controller = {
.name = "MSP_CIC",
.ack = ack_msp_cic_irq,
.mask = ack_msp_cic_irq,
.mask_ack = ack_msp_cic_irq,
.unmask = unmask_msp_cic_irq,
};
void __init msp_cic_irq_init(void)
{
int i;
/* Mask/clear interrupts. */
*CIC_VPE0_MSK_REG = 0x00000000;
*PER_INT_MSK_REG = 0x00000000;
*CIC_STS_REG = 0xFFFFFFFF;
*PER_INT_STS_REG = 0xFFFFFFFF;
#if defined(CONFIG_PMC_MSP7120_GW) || \
defined(CONFIG_PMC_MSP7120_EVAL)
/*
* The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
* These inputs map to EXT_INT_POL[6:4] inside the CIC.
* They are to be active low, level sensitive.
*/
*CIC_EXT_CFG_REG &= 0xFFFF8F8F;
#endif
/* initialize all the IRQ descriptors */
for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++)
set_irq_chip_and_handler(i, &msp_cic_irq_controller,
handle_level_irq);
}
void msp_cic_irq_dispatch(void)
{
u32 pending;
int intbase;
intbase = MSP_CIC_INTBASE;
pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG;
/* check for PER interrupt */
if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
intbase = MSP_PER_INTBASE;
pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
}
/* check for spurious interrupt */
if (pending == 0x00000000) {
printk(KERN_ERR
"Spurious %s interrupt? status %08x, mask %08x\n",
(intbase == MSP_CIC_INTBASE) ? "CIC" : "PER",
(intbase == MSP_CIC_INTBASE) ?
*CIC_STS_REG : *PER_INT_STS_REG,
(intbase == MSP_CIC_INTBASE) ?
*CIC_VPE0_MSK_REG : *PER_INT_MSK_REG);
return;
}
/* check for the timer and dispatch it first */
if ((intbase == MSP_CIC_INTBASE) &&
(pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))))
do_IRQ(MSP_INT_VPE0_TIMER);
else
do_IRQ(ffs(pending) + intbase - 1);
}
/*
* This file define the irq handler for MSP SLM subsystem interrupts.
*
* Copyright 2005-2006 PMC-Sierra, Inc, derived from irq_cpu.c
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <msp_slp_int.h>
#include <msp_regs.h>
static inline void unmask_msp_slp_irq(unsigned int irq)
{
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*SLP_INT_MSK_REG |= (1 << (irq - MSP_SLP_INTBASE));
else
*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
}
static inline void mask_msp_slp_irq(unsigned int irq)
{
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*SLP_INT_MSK_REG &= ~(1 << (irq - MSP_SLP_INTBASE));
else
*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
}
/*
* While we ack the interrupt interrupts are disabled and thus we don't need
* to deal with concurrency issues. Same for msp_slp_irq_end.
*/
static inline void ack_msp_slp_irq(unsigned int irq)
{
mask_slp_irq(irq);
/*
* only really necessary for 18, 16-14 and sometimes 3:0 (since
* these can be edge sensitive) but it doesn't hurt for the others.
*/
/* check for PER interrupt range */
if (irq < MSP_PER_INTBASE)
*SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE));
else
*PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
}
static struct irq_chip msp_slp_irq_controller = {
.name = "MSP_SLP",
.ack = ack_msp_slp_irq,
.mask = ack_msp_slp_irq,
.mask_ack = ack_msp_slp_irq,
.unmask = unmask_msp_slp_irq,
};
void __init msp_slp_irq_init(void)
{
int i;
/* Mask/clear interrupts. */
*SLP_INT_MSK_REG = 0x00000000;
*PER_INT_MSK_REG = 0x00000000;
*SLP_INT_STS_REG = 0xFFFFFFFF;
*PER_INT_STS_REG = 0xFFFFFFFF;
/* initialize all the IRQ descriptors */
for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++)
set_irq_chip_and_handler(i, &msp_slp_irq_controller
handle_level_irq);
}
void msp_slp_irq_dispatch(void)
{
u32 pending;
int intbase;
intbase = MSP_SLP_INTBASE;
pending = *SLP_INT_STS_REG & *SLP_INT_MSK_REG;
/* check for PER interrupt */
if (pending == (1 << (MSP_INT_PER - MSP_SLP_INTBASE))) {
intbase = MSP_PER_INTBASE;
pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
}
/* check for spurious interrupt */
if (pending == 0x00000000) {
printk(KERN_ERR "Spurious %s interrupt?\n",
(intbase == MSP_SLP_INTBASE) ? "SLP" : "PER");
return;
}
/* dispatch the irq */
do_IRQ(ffs(pending) + intbase - 1);
}
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/*
* The generic setup file for PMC-Sierra MSP processors
*
* Copyright 2005-2007 PMC-Sierra, Inc,
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <asm/bootinfo.h>
#include <asm/cacheflush.h>
#include <asm/r4kcache.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <msp_prom.h>
#include <msp_regs.h>
#if defined(CONFIG_PMC_MSP7120_GW)
#include <msp_regops.h>
#include <msp_gpio.h>
#define MSP_BOARD_RESET_GPIO 9
#endif
extern void msp_timer_init(void);
extern void msp_serial_setup(void);
extern void pmctwiled_setup(void);
#if defined(CONFIG_PMC_MSP7120_EVAL) || \
defined(CONFIG_PMC_MSP7120_GW) || \
defined(CONFIG_PMC_MSP7120_FPGA)
/*
* Performs the reset for MSP7120-based boards
*/
void msp7120_reset(void)
{
void *start, *end, *iptr;
register int i;
/* Diasble all interrupts */
local_irq_disable();
#ifdef CONFIG_SYS_SUPPORTS_MULTITHREADING
dvpe();
#endif
/* Cache the reset code of this function */
__asm__ __volatile__ (
" .set push \n"
" .set mips3 \n"
" la %0,startpoint \n"
" la %1,endpoint \n"
" .set pop \n"
: "=r" (start), "=r" (end)
:
);
for (iptr = (void *)((unsigned int)start & ~(L1_CACHE_BYTES - 1));
iptr < end; iptr += L1_CACHE_BYTES)
cache_op(Fill, iptr);
__asm__ __volatile__ (
"startpoint: \n"
);
/* Put the DDRC into self-refresh mode */
DDRC_INDIRECT_WRITE(DDRC_CTL(10), 0xb, 1 << 16);
/*
* IMPORTANT!
* DO NOT do anything from here on out that might even
* think about fetching from RAM - i.e., don't call any
* non-inlined functions, and be VERY sure that any inline
* functions you do call do NOT access any sort of RAM
* anywhere!
*/
/* Wait a bit for the DDRC to settle */
for (i = 0; i < 100000000; i++);
#if defined(CONFIG_PMC_MSP7120_GW)
/*
* Set GPIO 9 HI, (tied to board reset logic)
* GPIO 9 is the 4th GPIO of register 3
*
* NOTE: We cannot use the higher-level msp_gpio_mode()/out()
* as GPIO char driver may not be enabled and it would look up
* data inRAM!
*/
set_value_reg32(GPIO_CFG3_REG,
basic_mode_mask(MSP_BOARD_RESET_GPIO),
basic_mode(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO));
set_reg32(GPIO_DATA3_REG,
basic_data_mask(MSP_BOARD_RESET_GPIO));
/*
* In case GPIO9 doesn't reset the board (jumper configurable!)
* fallback to device reset below.
*/
#endif
/* Set bit 1 of the MSP7120 reset register */
*RST_SET_REG = 0x00000001;
__asm__ __volatile__ (
"endpoint: \n"
);
}
#endif
void msp_restart(char *command)
{
printk(KERN_WARNING "Now rebooting .......\n");
#if defined(CONFIG_PMC_MSP7120_EVAL) || \
defined(CONFIG_PMC_MSP7120_GW) || \
defined(CONFIG_PMC_MSP7120_FPGA)
msp7120_reset();
#else
/* No chip-specific reset code, just jump to the ROM reset vector */
set_c0_status(ST0_BEV | ST0_ERL);
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_c0_wired(0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
#endif
}
void msp_halt(void)
{
printk(KERN_WARNING "\n** You can safely turn off the power\n");
while (1)
/* If possible call official function to get CPU WARs */
if (cpu_wait)
(*cpu_wait)();
else
__asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
}
void msp_power_off(void)
{
msp_halt();
}
void __init plat_mem_setup(void)
{
_machine_restart = msp_restart;
_machine_halt = msp_halt;
pm_power_off = msp_power_off;
board_time_init = msp_timer_init;
}
void __init prom_init(void)
{
unsigned long family;
unsigned long revision;
prom_argc = fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;
/*
* Someday we can use this with PMON2000 to get a
* platform call prom routines for output etc. without
* having to use grody hacks. For now it's unused.
*
* struct callvectors *cv = (struct callvectors *) fw_arg3;
*/
family = identify_family();
revision = identify_revision();
switch (family) {
case FAMILY_FPGA:
if (FPGA_IS_MSP4200(revision)) {
/* Old-style revision ID */
mips_machgroup = MACH_GROUP_MSP;
mips_machtype = MACH_MSP4200_FPGA;
} else {
mips_machgroup = MACH_GROUP_MSP;
mips_machtype = MACH_MSP_OTHER;
}
break;
case FAMILY_MSP4200:
mips_machgroup = MACH_GROUP_MSP;
#if defined(CONFIG_PMC_MSP4200_EVAL)
mips_machtype = MACH_MSP4200_EVAL;
#elif defined(CONFIG_PMC_MSP4200_GW)
mips_machtype = MACH_MSP4200_GW;
#else
mips_machtype = MACH_MSP_OTHER;
#endif
break;
case FAMILY_MSP4200_FPGA:
mips_machgroup = MACH_GROUP_MSP;
mips_machtype = MACH_MSP4200_FPGA;
break;
case FAMILY_MSP7100:
mips_machgroup = MACH_GROUP_MSP;
#if defined(CONFIG_PMC_MSP7120_EVAL)
mips_machtype = MACH_MSP7120_EVAL;
#elif defined(CONFIG_PMC_MSP7120_GW)
mips_machtype = MACH_MSP7120_GW;
#else
mips_machtype = MACH_MSP_OTHER;
#endif
break;
case FAMILY_MSP7100_FPGA:
mips_machgroup = MACH_GROUP_MSP;
mips_machtype = MACH_MSP7120_FPGA;
break;
default:
/* we don't recognize the machine */
mips_machgroup = MACH_GROUP_UNKNOWN;
mips_machtype = MACH_UNKNOWN;
break;
}
/* make sure we have the right initialization routine - sanity */
if (mips_machgroup != MACH_GROUP_MSP) {
ppfinit("Unknown machine group in a "
"MSP initialization routine\n");
panic("***Bogosity factor five***, exiting\n");
}
prom_init_cmdline();
prom_meminit();
/*
* Sub-system setup follows.
* Setup functions can either be called here or using the
* subsys_initcall mechanism (i.e. see msp_pci_setup). The
* order in which they are called can be changed by using the
* link order in arch/mips/pmc-sierra/msp71xx/Makefile.
*
* NOTE: Please keep sub-system specific initialization code
* in separate specific files.
*/
msp_serial_setup();
#ifdef CONFIG_PMCTWILED
/*
* Setup LED states before the subsys_initcall loads other
* dependant drivers/modules.
*/
pmctwiled_setup();
#endif
}
/*
* Setting up the clock on MSP SOCs. No RTC typically.
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*/
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/ptrace.h>
#include <asm/mipsregs.h>
#include <asm/time.h>
#include <msp_prom.h>
#include <msp_int.h>
#include <msp_regs.h>
void __init msp_timer_init(void)
{
char *endp, *s;
unsigned long cpu_rate = 0;
if (cpu_rate == 0) {
s = prom_getenv("clkfreqhz");
cpu_rate = simple_strtoul(s, &endp, 10);
if (endp != NULL && *endp != 0) {
printk(KERN_ERR
"Clock rate in Hz parse error: %s\n", s);
cpu_rate = 0;
}
}
if (cpu_rate == 0) {
s = prom_getenv("clkfreq");
cpu_rate = 1000 * simple_strtoul(s, &endp, 10);
if (endp != NULL && *endp != 0) {
printk(KERN_ERR
"Clock rate in MHz parse error: %s\n", s);
cpu_rate = 0;
}
}
if (cpu_rate == 0) {
#if defined(CONFIG_PMC_MSP7120_EVAL) \
|| defined(CONFIG_PMC_MSP7120_GW)
cpu_rate = 400000000;
#elif defined(CONFIG_PMC_MSP7120_FPGA)
cpu_rate = 25000000;
#else
cpu_rate = 150000000;
#endif
printk(KERN_ERR
"Failed to determine CPU clock rate, "
"assuming %ld hz ...\n", cpu_rate);
}
printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate);
/* timer frequency is 1/2 clock rate */
mips_hpt_frequency = cpu_rate/2;
}
void __init plat_timer_setup(struct irqaction *irq)
{
#ifdef CONFIG_IRQ_MSP_CIC
/* we are using the vpe0 counter for timer interrupts */
setup_irq(MSP_INT_VPE0_TIMER, irq);
#else
/* we are using the mips counter for timer interrupts */
setup_irq(MSP_INT_TIMER, irq);
#endif
}
/*
* The setup file for USB related hardware on PMC-Sierra MSP processors.
*
* Copyright 2006-2007 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <asm/mipsregs.h>
#include <msp_regs.h>
#include <msp_int.h>
#include <msp_prom.h>
#if defined(CONFIG_USB_EHCI_HCD)
static struct resource msp_usbhost_resources [] = {
[0] = {
.start = MSP_USB_BASE_START,
.end = MSP_USB_BASE_END,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MSP_INT_USB,
.end = MSP_INT_USB,
.flags = IORESOURCE_IRQ,
},
};
static u64 msp_usbhost_dma_mask = DMA_32BIT_MASK;
static struct platform_device msp_usbhost_device = {
.name = "pmcmsp-ehci",
.id = 0,
.dev = {
.dma_mask = &msp_usbhost_dma_mask,
.coherent_dma_mask = DMA_32BIT_MASK,
},
.num_resources = ARRAY_SIZE (msp_usbhost_resources),
.resource = msp_usbhost_resources,
};
#endif /* CONFIG_USB_EHCI_HCD */
#if defined(CONFIG_USB_GADGET)
static struct resource msp_usbdev_resources [] = {
[0] = {
.start = MSP_USB_BASE,
.end = MSP_USB_BASE_END,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MSP_INT_USB,
.end = MSP_INT_USB,
.flags = IORESOURCE_IRQ,
},
};
static u64 msp_usbdev_dma_mask = DMA_32BIT_MASK;
static struct platform_device msp_usbdev_device = {
.name = "msp71xx_udc",
.id = 0,
.dev = {
.dma_mask = &msp_usbdev_dma_mask,
.coherent_dma_mask = DMA_32BIT_MASK,
},
.num_resources = ARRAY_SIZE (msp_usbdev_resources),
.resource = msp_usbdev_resources,
};
#endif /* CONFIG_USB_GADGET */
#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET)
static struct platform_device *msp_devs[1];
#endif
static int __init msp_usb_setup(void)
{
#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET)
char *strp;
char envstr[32];
unsigned int val = 0;
int result = 0;
/*
* construct environment name usbmode
* set usbmode <host/device> as pmon environment var
*/
snprintf((char *)&envstr[0], sizeof(envstr), "usbmode");
#if defined(CONFIG_USB_EHCI_HCD)
/* default to host mode */
val = 1;
#endif
/* get environment string */
strp = prom_getenv((char *)&envstr[0]);
if (strp) {
if (!strcmp(strp, "device"))
val = 0;
}
if (val) {
#if defined(CONFIG_USB_EHCI_HCD)
/* get host mode device */
msp_devs[0] = &msp_usbhost_device;
ppfinit("platform add USB HOST done %s.\n",
msp_devs[0]->name);
result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs));
#endif /* CONFIG_USB_EHCI_HCD */
}
#if defined(CONFIG_USB_GADGET)
else {
/* get device mode structure */
msp_devs[0] = &msp_usbdev_device;
ppfinit("platform add USB DEVICE done %s.\n",
msp_devs[0]->name);
result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs));
}
#endif /* CONFIG_USB_GADGET */
#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */
return result;
}
subsys_initcall(msp_usb_setup);
/*
* Defines for the MSP interrupt controller.
*
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*/
#ifndef _MSP_CIC_INT_H
#define _MSP_CIC_INT_H
/*
* The PMC-Sierra CIC interrupts are all centrally managed by the
* CIC sub-system.
* We attempt to keep the interrupt numbers as consistent as possible
* across all of the MSP devices, but some differences will creep in ...
* The interrupts which are directly forwarded to the MIPS core interrupts
* are assigned interrupts in the range 0-7, interrupts cascaded through
* the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
* (MSP_INT_CIC). Currently we don't really distinguish between VPE1
* and VPE0 (or thread contexts for that matter). Will have to fix.
* The PER interrupts are assigned interrupts in the range 40-71.
*/
/*
* IRQs directly forwarded to the CPU
*/
#define MSP_MIPS_INTBASE 0
#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
/*
* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
* These defines should be tied to the register definitions for the CIC
* interrupt routine. For now, just use hard-coded values.
*/
#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
/* External interrupt 0 */
#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
/* External interrupt 1 */
#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
/* External interrupt 2 */
#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
/* External interrupt 3 */
#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
/* CPU interface interrupt */
#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
/* External interrupt 4 */
#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
/* Cascaded IRQ for USB */
#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
/* Sec engine mailbox IRQ */
#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
/* External interrupt 5 */
#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
/* TDM interrupt */
#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
/* Cascaded IRQ for MAC 0 */
#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
/* Cascaded IRQ for MAC 1 */
#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
/* Cascaded IRQ for sec engine */
#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
/* Peripheral interrupt */
#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
/* SLP timer 0 */
#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
/* SLP timer 1 */
#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
/* SLP timer 2 */
#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
/* VPE0 MIPS timer */
#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
/* Block Copy */
#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
/* UART 0 */
#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
/* PCI subsystem */
#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
/* External interrupt 5 */
#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
/* PCI Message Signal */
#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
/* Cascaded ADSL2+ SAR IRQ */
#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
/* ADSL2+ IRQ */
#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
/* SLP error condition */
#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
/* VPE1 MIPS timer */
#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
/* VPE0 Performance counter */
#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
/* VPE1 Performance counter */
#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
/* External interrupt 5 */
#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
/* VPE0 Software interrupt */
#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
/* VPE0 Software interrupt */
/*
* IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
*/
#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
/* Reserved 0-1 */
#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
/* UART 1 */
/* Reserved 3-5 */
#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
/* 2-wire */
#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
/* Peripheral timer block out 0 */
#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
/* Peripheral timer block out 1 */
/* Reserved 9 */
#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
/* SPI RX complete */
#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
/* SPI TX complete */
#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
/* GPIO */
#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
/* Peripheral error */
/* Reserved 14-31 */
#endif /* !_MSP_CIC_INT_H */
/*
* Defines for the MSP interrupt handlers.
*
* Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved.
* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*/
#ifndef _MSP_INT_H
#define _MSP_INT_H
/*
* The PMC-Sierra MSP product line has at least two different interrupt
* controllers, the SLP register based scheme and the CIC interrupt
* controller block mechanism. This file distinguishes between them
* so that devices see a uniform interface.
*/
#if defined(CONFIG_IRQ_MSP_SLP)
#include "msp_slp_int.h"
#elif defined(CONFIG_IRQ_MSP_CIC)
#include "msp_cic_int.h"
#else
#error "What sort of interrupt controller does *your* MSP have?"
#endif
#endif /* !_MSP_INT_H */
/*
* MIPS boards bootprom interface for the Linux kernel.
*
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*/
#ifndef _ASM_MSP_PROM_H
#define _ASM_MSP_PROM_H
#include <linux/types.h>
#define DEVICEID "deviceid"
#define FEATURES "features"
#define PROM_ENV "prom_env"
#define PROM_ENV_FILE "/proc/"PROM_ENV
#define PROM_ENV_SIZE 256
#define CPU_DEVID_FAMILY 0x0000ff00
#define CPU_DEVID_REVISION 0x000000ff
#define FPGA_IS_POLO(revision) \
(((revision >= 0xb0) && (revision < 0xd0)))
#define FPGA_IS_5000(revision) \
((revision >= 0x80) && (revision <= 0x90))
#define FPGA_IS_ZEUS(revision) ((revision < 0x7f))
#define FPGA_IS_DUET(revision) \
(((revision >= 0xa0) && (revision < 0xb0)))
#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0))
#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0))
#define MACHINE_TYPE_POLO "POLO"
#define MACHINE_TYPE_DUET "DUET"
#define MACHINE_TYPE_ZEUS "ZEUS"
#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB"
#define MACHINE_TYPE_MSP5000 "MSP5000"
#define MACHINE_TYPE_MSP4200 "MSP4200"
#define MACHINE_TYPE_MSP7120 "MSP7120"
#define MACHINE_TYPE_MSP7130 "MSP7130"
#define MACHINE_TYPE_OTHER "OTHER"
#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA"
#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
/* Device Family definitions */
#define FAMILY_FPGA 0x0000
#define FAMILY_ZEUS 0x1000
#define FAMILY_POLO 0x2000
#define FAMILY_DUET 0x4000
#define FAMILY_TRIAD 0x5000
#define FAMILY_MSP4200 0x4200
#define FAMILY_MSP4200_FPGA 0x4f00
#define FAMILY_MSP7100 0x7100
#define FAMILY_MSP7100_FPGA 0x7f00
/* Device Type definitions */
#define TYPE_MSP7120 0x7120
#define TYPE_MSP7130 0x7130
#define ENET_KEY 'E'
#define ENETTXD_KEY 'e'
#define PCI_KEY 'P'
#define PCIMUX_KEY 'p'
#define SEC_KEY 'S'
#define SPAD_KEY 'D'
#define TDM_KEY 'T'
#define ZSP_KEY 'Z'
#define FEATURE_NOEXIST '-'
#define FEATURE_EXIST '+'
#define ENET_MII 'M'
#define ENET_RMII 'R'
#define ENETTXD_FALLING 'F'
#define ENETTXD_RISING 'R'
#define PCI_HOST 'H'
#define PCI_PERIPHERAL 'P'
#define PCIMUX_FULL 'F'
#define PCIMUX_SINGLE 'S'
#define SEC_DUET 'D'
#define SEC_POLO 'P'
#define SEC_SLOW 'S'
#define SEC_TRIAD 'T'
#define SPAD_POLO 'P'
#define TDM_DUET 'D' /* DUET TDMs might exist */
#define TDM_POLO 'P' /* POLO TDMs might exist */
#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */
#define ZSP_DUET 'D' /* one DUET zsp engine */
#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
extern char *prom_getcmdline(void);
extern char *prom_getenv(char *name);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem,
unsigned long end_mem);
#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
extern bool get_ramroot(void **start, unsigned long *size);
#endif
extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
extern unsigned long get_deviceid(void);
extern char identify_enet(unsigned long interface_num);
extern char identify_enetTxD(unsigned long interface_num);
extern char identify_pci(void);
extern char identify_sec(void);
extern char identify_spad(void);
extern char identify_sec(void);
extern char identify_tdm(void);
extern char identify_zsp(void);
extern unsigned long identify_family(void);
extern unsigned long identify_revision(void);
/*
* The following macro calls prom_printf and puts the format string
* into an init section so it can be reclaimed.
*/
#define ppfinit(f, x...) \
do { \
static char _f[] __initdata = KERN_INFO f; \
printk(_f, ## x); \
} while (0)
/* Memory descriptor management. */
#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */
enum yamon_memtypes {
yamon_dontuse,
yamon_prom,
yamon_free,
};
struct prom_pmemblock {
unsigned long base; /* Within KSEG0. */
unsigned int size; /* In bytes. */
unsigned int type; /* free or prom memory */
};
extern int prom_argc;
extern char **prom_argv;
extern char **prom_envp;
extern int *prom_vec;
extern struct prom_pmemblock *prom_getmdesc(void);
#endif /* !_ASM_MSP_PROM_H */
/*
* SMP/VPE-safe functions to access "registers" (see note).
*
* NOTES:
* - These macros use ll/sc instructions, so it is your responsibility to
* ensure these are available on your platform before including this file.
* - The MIPS32 spec states that ll/sc results are undefined for uncached
* accesses. This means they can't be used on HW registers accessed
* through kseg1. Code which requires these macros for this purpose must
* front-end the registers with cached memory "registers" and have a single
* thread update the actual HW registers.
* - A maximum of 2k of code can be inserted between ll and sc. Every
* memory accesses between the instructions will increase the chance of
* sc failing and having to loop.
* - When using custom_read_reg32/custom_write_reg32 only perform the
* necessary logical operations on the register value in between these
* two calls. All other logic should be performed before the first call.
* - There is a bug on the R10000 chips which has a workaround. If you
* are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
* to be non-zero. If you are using this header from within linux, you may
* include <asm/war.h> before including this file to have this defined
* appropriately for you.
*
* Copyright 2005-2007 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc., 675
* Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_REGOPS_H__
#define __ASM_REGOPS_H__
#include <linux/types.h>
#include <asm/war.h>
#ifndef R10000_LLSC_WAR
#define R10000_LLSC_WAR 0
#endif
#if R10000_LLSC_WAR == 1
#define __beqz "beqzl "
#else
#define __beqz "beqz "
#endif
#ifndef _LINUX_TYPES_H
typedef unsigned int u32;
#endif
/*
* Sets all the masked bits to the corresponding value bits
*/
static inline void set_value_reg32(volatile u32 *const addr,
u32 const mask,
u32 const value)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set mips3 \n"
"1: ll %0, %1 # set_value_reg32 \n"
" and %0, %2 \n"
" or %0, %3 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=m" (*addr)
: "ir" (~mask), "ir" (value), "m" (*addr));
}
/*
* Sets all the masked bits to '1'
*/
static inline void set_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set mips3 \n"
"1: ll %0, %1 # set_reg32 \n"
" or %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=m" (*addr)
: "ir" (mask), "m" (*addr));
}
/*
* Sets all the masked bits to '0'
*/
static inline void clear_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set mips3 \n"
"1: ll %0, %1 # clear_reg32 \n"
" and %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=m" (*addr)
: "ir" (~mask), "m" (*addr));
}
/*
* Toggles all masked bits from '0' to '1' and '1' to '0'
*/
static inline void toggle_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set mips3 \n"
"1: ll %0, %1 # toggle_reg32 \n"
" xor %0, %2 \n"
" sc %0, %1 \n"
" "__beqz"%0, 1b \n"
" nop \n"
" .set pop \n"
: "=&r" (temp), "=m" (*addr)
: "ir" (mask), "m" (*addr));
}
/*
* Read all masked bits others are returned as '0'
*/
static inline u32 read_reg32(volatile u32 *const addr,
u32 const mask)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" lw %0, %1 # read \n"
" and %0, %2 # mask \n"
" .set pop \n"
: "=&r" (temp)
: "m" (*addr), "ir" (mask));
return temp;
}
/*
* blocking_read_reg32 - Read address with blocking load
*
* Uncached writes need to be read back to ensure they reach RAM.
* The returned value must be 'used' to prevent from becoming a
* non-blocking load.
*/
static inline u32 blocking_read_reg32(volatile u32 *const addr)
{
u32 temp;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" lw %0, %1 # read \n"
" move %0, %0 # block \n"
" .set pop \n"
: "=&r" (temp)
: "m" (*addr));
return temp;
}
/*
* For special strange cases only:
*
* If you need custom processing within a ll/sc loop, use the following macros
* VERY CAREFULLY:
*
* u32 tmp; <-- Define a variable to hold the data
*
* custom_read_reg32(address, tmp); <-- Reads the address and put the value
* in the 'tmp' variable given
*
* From here on out, you are (basicly) atomic, so don't do anything too
* fancy!
* Also, this code may loop if the end of this block fails to write
* everything back safely due do the other CPU, so do NOT do anything
* with side-effects!
*
* custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
*/
#define custom_read_reg32(address, tmp) \
__asm__ __volatile__( \
" .set push \n" \
" .set mips3 \n" \
"1: ll %0, %1 #custom_read_reg32 \n" \
" .set pop \n" \
: "=r" (tmp), "=m" (*address) \
: "m" (*address))
#define custom_write_reg32(address, tmp) \
__asm__ __volatile__( \
" .set push \n" \
" .set mips3 \n" \
" sc %0, %1 #custom_write_reg32 \n" \
" "__beqz"%0, 1b \n" \
" nop \n" \
" .set pop \n" \
: "=&r" (tmp), "=m" (*address) \
: "0" (tmp), "m" (*address))
#endif /* __ASM_REGOPS_H__ */
This diff is collapsed.
/*
* Defines for the MSP interrupt controller.
*
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
* Author: Carsten Langgaard, carstenl@mips.com
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*/
#ifndef _MSP_SLP_INT_H
#define _MSP_SLP_INT_H
/*
* The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
* hierarchical system. The first level are the direct MIPS interrupts
* and are assigned the interrupt range 0-7. The second level is the SLM
* interrupt controller and is assigned the range 8-39. The third level
* comprises the Peripherial block, the PCI block, the PCI MSI block and
* the SLP. The PCI interrupts and the SLP errors are handled by the
* relevant subsystems so the core interrupt code needs only concern
* itself with the Peripheral block. These are assigned interrupts in
* the range 40-71.
*/
/*
* IRQs directly connected to CPU
*/
#define MSP_MIPS_INTBASE 0
#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
/*
* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
* These defines should be tied to the register definition for the SLM
* interrupt routine. For now, just use hard-coded values.
*/
#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
/* External interrupt 0 */
#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
/* External interrupt 1 */
#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
/* External interrupt 2 */
#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
/* External interrupt 3 */
/* Reserved 4-7 */
/*
*************************************************************************
* DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
* Some MSP produces have this interrupt labelled as Voice and some are *
* SEC mbox ... *
*************************************************************************
*/
#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
/* Cascaded IRQ for Voice Engine*/
#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
/* TDM interrupt */
#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
/* Cascaded IRQ for MAC 0 */
#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
/* Cascaded IRQ for MAC 1 */
#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
/* IRQ for security engine */
#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
/* Peripheral interrupt */
#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
/* SLP timer 0 */
#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
/* SLP timer 1 */
#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
/* SLP timer 2 */
#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
/* Cascaded MIPS timer */
#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
/* Block Copy */
#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
/* UART 0 */
#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
/* PCI subsystem */
#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
/* PCI doorbell */
#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
/* PCI Message Signal */
#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
/* PCI Block Copy 0 */
#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
/* PCI Block Copy 1 */
#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
/* SLP error condition */
#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
/* IRQ for MAC2 */
/* Reserved 26-31 */
/*
* IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
*/
#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
/* Reserved 0-1 */
#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
/* UART 1 */
/* Reserved 3-5 */
#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
/* 2-wire */
#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
/* Peripheral timer block out 0 */
#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
/* Peripheral timer block out 1 */
/* Reserved 9 */
#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
/* SPI RX complete */
#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
/* SPI TX complete */
#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
/* GPIO */
#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
/* Peripheral error */
/* Reserved 14-31 */
#endif /* !_MSP_SLP_INT_H */
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