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Commit 35ce37d6 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: Enable ipp compilation 

Update relevant registers
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 13066f9f
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Showing with 54 additions and 62 deletions
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
View file @ 35ce37d6
......@@ -421,7 +421,10 @@ static void dcn10_ipp_enable_cm_block(
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
if (ippn10->ipp_mask->CM_BYPASS_EN)
REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
else
REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
}
......@@ -484,7 +487,7 @@ static bool dcn10_cursor_program_control(
REG_UPDATE_2(CURSOR0_CONTROL,
CUR0_MODE, color_format,
CUR0_INVERT_MODE, 0);
CUR0_EXPANSION_MODE, 0);
if (color_format == CURSOR_MODE_MONO) {
/* todo: clarify what to program these to */
......@@ -501,18 +504,6 @@ static bool dcn10_cursor_program_control(
ALPHA_EN, 1,
FORMAT_EXPANSION_MODE, 0);
REG_UPDATE(CURSOR0_CONTROL,
CUR0_EXPANSION_MODE, 0);
if (0 /*attributes->attribute_flags.bits.MIN_MAX_INVERT*/) {
REG_UPDATE(CURSOR0_CONTROL,
CUR0_MAX,
0 /* TODO */);
REG_UPDATE(CURSOR0_CONTROL,
CUR0_MIN,
0 /* TODO */);
}
return true;
}
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
View file @ 35ce37d6
......@@ -31,7 +31,7 @@
#define TO_DCN10_IPP(ipp)\
container_of(ipp, struct dcn10_ipp, base)
#define IPP_DCN10_REG_LIST(id) \
#define IPP_REG_LIST_DCN(id) \
SRI(CM_ICSC_CONTROL, CM, id), \
SRI(CM_ICSC_C11_C12, CM, id), \
SRI(CM_ICSC_C13_C14, CM, id), \
......@@ -39,12 +39,6 @@
SRI(CM_ICSC_C23_C24, CM, id), \
SRI(CM_ICSC_C31_C32, CM, id), \
SRI(CM_ICSC_C33_C34, CM, id), \
SRI(CM_COMA_C11_C12, CM, id), \
SRI(CM_COMA_C13_C14, CM, id), \
SRI(CM_COMA_C21_C22, CM, id), \
SRI(CM_COMA_C23_C24, CM, id), \
SRI(CM_COMA_C31_C32, CM, id), \
SRI(CM_COMA_C33_C34, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
......@@ -86,22 +80,31 @@
SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_DGAM_LUT_INDEX, CM, id), \
SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(CM_DGAM_CONTROL, CM, id), \
SRI(CM_IGAM_CONTROL, CM, id), \
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(DPP_CONTROL, DPP_TOP, id), \
SRI(CURSOR_SETTINS, HUBPREQ, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(CURSOR0_COLOR1, CNVC_CUR, id)
#define IPP_REG_LIST_DCN10(id) \
IPP_REG_LIST_DCN(id), \
SRI(CM_IGAM_CONTROL, CM, id), \
SRI(CM_COMA_C11_C12, CM, id), \
SRI(CM_COMA_C13_C14, CM, id), \
SRI(CM_COMA_C21_C22, CM, id), \
SRI(CM_COMA_C23_C24, CM, id), \
SRI(CM_COMA_C31_C32, CM, id), \
SRI(CM_COMA_C33_C34, CM, id), \
SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
SRI(CURSOR_SIZE, CURSOR, id), \
......@@ -113,7 +116,7 @@
#define IPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define IPP_DCN10_MASK_SH_LIST(mask_sh) \
#define IPP_MASK_SH_LIST_DCN(mask_sh) \
IPP_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
......@@ -127,18 +130,6 @@
IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C32, mask_sh), \
IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \
IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \
IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \
IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh), \
IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh), \
IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh), \
IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh), \
IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh), \
IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh), \
IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh), \
IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh), \
IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
......@@ -240,37 +231,46 @@
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
IPP_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
IPP_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_INVERT_MODE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MAX, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MIN, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh)
#define IPP_MASK_SH_LIST_DCN10(mask_sh) \
IPP_MASK_SH_LIST_DCN(mask_sh),\
IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \
IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \
IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \
IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh), \
IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh), \
IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh), \
IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh), \
IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh), \
IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh), \
IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh), \
IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh), \
IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
IPP_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
IPP_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
......@@ -279,12 +279,15 @@
IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
......@@ -431,6 +434,7 @@
type CM_DGAM_LUT_DATA; \
type DPP_CLOCK_ENABLE; \
type CM_BYPASS_EN; \
type CM_BYPASS; \
type CNVC_SURFACE_PIXEL_FORMAT; \
type CNVC_BYPASS; \
type ALPHA_EN; \
......@@ -440,12 +444,9 @@
type CURSOR0_DST_Y_OFFSET; \
type CURSOR0_CHUNK_HDL_ADJUST; \
type CUR0_MODE; \
type CUR0_INVERT_MODE; \
type CUR0_COLOR0; \
type CUR0_COLOR1; \
type CUR0_EXPANSION_MODE; \
type CUR0_MAX; \
type CUR0_MIN; \
type CURSOR_SURFACE_ADDRESS_HIGH; \
type CURSOR_SURFACE_ADDRESS; \
type CURSOR_WIDTH; \
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View file @ 35ce37d6
......@@ -266,7 +266,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {
#define ipp_regs(id)\
[id] = {\
IPP_DCN10_REG_LIST(id),\
IPP_REG_LIST_DCN10(id),\
}
static const struct dcn10_ipp_registers ipp_regs[] = {
......@@ -277,11 +277,11 @@ static const struct dcn10_ipp_registers ipp_regs[] = {
};
static const struct dcn10_ipp_shift ipp_shift = {
IPP_DCN10_MASK_SH_LIST(__SHIFT)
IPP_MASK_SH_LIST_DCN10(__SHIFT)
};
static const struct dcn10_ipp_mask ipp_mask = {
IPP_DCN10_MASK_SH_LIST(_MASK),
IPP_MASK_SH_LIST_DCN10(_MASK),
};
#define opp_regs(id)\
......
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