Commit 37af2f30 authored by James Hogan's avatar James Hogan Committed by Ralf Baechle

MIPS: Define & use CP0_EBase bit definitions

Add definitions for the bits & fields in the CP0_EBase register, and use
them from a few different places in arch/mips which hardcoded these
values.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13222/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent dc3ee608
...@@ -676,6 +676,14 @@ ...@@ -676,6 +676,14 @@
#define MIPS_MAAR_S (_ULCAST_(1) << 1) #define MIPS_MAAR_S (_ULCAST_(1) << 1)
#define MIPS_MAAR_V (_ULCAST_(1) << 0) #define MIPS_MAAR_V (_ULCAST_(1) << 0)
/* EBase bit definitions */
#define MIPS_EBASE_CPUNUM_SHIFT 0
#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
#define MIPS_EBASE_WG_SHIFT 11
#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
#define MIPS_EBASE_BASE_SHIFT 12
#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
/* CMGCRBase bit definitions */ /* CMGCRBase bit definitions */
#define MIPS_CMGCRB_BASE 11 #define MIPS_CMGCRB_BASE 11
#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
...@@ -2104,7 +2112,7 @@ __BUILD_SET_C0(brcm_mode) ...@@ -2104,7 +2112,7 @@ __BUILD_SET_C0(brcm_mode)
*/ */
static inline unsigned int get_ebase_cpunum(void) static inline unsigned int get_ebase_cpunum(void)
{ {
return read_c0_ebase() & 0x3ff; return read_c0_ebase() & MIPS_EBASE_CPUNUM;
} }
#endif /* !__ASSEMBLY__ */ #endif /* !__ASSEMBLY__ */
......
...@@ -505,7 +505,8 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu) ...@@ -505,7 +505,8 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
kvm_write_c0_guest_intctl(cop0, 0xFC000000); kvm_write_c0_guest_intctl(cop0, 0xFC000000);
/* Put in vcpu id as CPUNum into Ebase Reg to handle SMP Guests */ /* Put in vcpu id as CPUNum into Ebase Reg to handle SMP Guests */
kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 | (vcpu_id & 0xFF)); kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 |
(vcpu_id & MIPS_EBASE_CPUNUM));
return 0; return 0;
} }
......
...@@ -58,7 +58,7 @@ void nlm_node_init(int node) ...@@ -58,7 +58,7 @@ void nlm_node_init(int node)
nodep->coremask = 1; /* node 0, boot cpu */ nodep->coremask = 1; /* node 0, boot cpu */
nodep->sysbase = nlm_get_sys_regbase(node); nodep->sysbase = nlm_get_sys_regbase(node);
nodep->picbase = nlm_get_pic_regbase(node); nodep->picbase = nlm_get_pic_regbase(node);
nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE;
if (cpu_is_xlp9xx()) if (cpu_is_xlp9xx())
nodep->socbus = xlp9xx_get_socbus(node); nodep->socbus = xlp9xx_get_socbus(node);
else else
......
...@@ -168,7 +168,7 @@ static void nlm_init_node(void) ...@@ -168,7 +168,7 @@ static void nlm_init_node(void)
nodep = nlm_current_node(); nodep = nlm_current_node();
nodep->picbase = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET); nodep->picbase = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE;
spin_lock_init(&nodep->piclock); spin_lock_init(&nodep->piclock);
} }
......
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