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Commit 3846e6a0 authored by Linus Walleij's avatar Linus Walleij
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Merge tag 'sh-pfc-for-v5.2-tag1' of... 

Merge tag 'sh-pfc-for-v5.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.2

  - Add HSCIF (serial) pin groups on R-Car H1,
  - Add I2C[035] pin groups on R-Car M3-N,
  - Add CANFD pin groups on RZ/G2M and RZ/G2E,
  - Retain SDHI/MMC clock return path delay configuration across
    suspend/resume on R-Car Gen3,
  - More validation of pinmux tables at build and runtime, including
    compile-test coverage of all drivers,
  - Small fixes, improvements, and cleanups.
parents d1ff8d07 0a042b35
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arch/sh/include/cpu-sh4/cpu/sh7786.h
View file @ 3846e6a0
......@@ -132,7 +132,7 @@ enum {
static inline u32 sh7786_mm_sel(void)
{
return __raw_readl(0xFC400020) & 0x7;
return __raw_readl((const volatile void __iomem *)0xFC400020) & 0x7;
}
#endif /* __CPU_SH7786_H__ */
drivers/pinctrl/pinctrl-rza1.c
View file @ 3846e6a0
......@@ -620,14 +620,7 @@ static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
static inline int rza1_pin_get_direction(struct rza1_port *port,
unsigned int pin)
{
unsigned long irqflags;
int input;
spin_lock_irqsave(&port->lock, irqflags);
input = rza1_get_bit(port, RZA1_PM_REG, pin);
spin_unlock_irqrestore(&port->lock, irqflags);
return !!input;
return !!rza1_get_bit(port, RZA1_PM_REG, pin);
}
/**
......@@ -671,14 +664,7 @@ static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
{
unsigned long irqflags;
int val;
spin_lock_irqsave(&port->lock, irqflags);
val = rza1_get_bit(port, RZA1_PPR_REG, pin);
spin_unlock_irqrestore(&port->lock, irqflags);
return val;
return rza1_get_bit(port, RZA1_PPR_REG, pin);
}
/**
......
drivers/pinctrl/sh-pfc/Kconfig
View file @ 3846e6a0
......@@ -3,201 +3,183 @@
# Renesas SH and SH Mobile PINCTRL drivers
#
if ARCH_RENESAS || SUPERH
config PINCTRL_SH_PFC
bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
default y if ARCH_RENESAS || SUPERH
select PINMUX
select PINCONF
select GENERIC_PINCONF
def_bool y
select PINCTRL_PFC_EMEV2 if ARCH_EMEV2
select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4
select PINCTRL_PFC_R8A7740 if ARCH_R8A7740
select PINCTRL_PFC_R8A7743 if ARCH_R8A7743
select PINCTRL_PFC_R8A7744 if ARCH_R8A7744
select PINCTRL_PFC_R8A7745 if ARCH_R8A7745
select PINCTRL_PFC_R8A77470 if ARCH_R8A77470
select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1
select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0
select PINCTRL_PFC_R8A7778 if ARCH_R8A7778
select PINCTRL_PFC_R8A7779 if ARCH_R8A7779
select PINCTRL_PFC_R8A7790 if ARCH_R8A7790
select PINCTRL_PFC_R8A7791 if ARCH_R8A7791
select PINCTRL_PFC_R8A7792 if ARCH_R8A7792
select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
select PINCTRL_PFC_R8A7796 if ARCH_R8A7796
select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
select PINCTRL_PFC_SH73A0 if ARCH_SH73A0
select PINCTRL_PFC_SH7720 if CPU_SUBTYPE_SH7720
select PINCTRL_PFC_SH7722 if CPU_SUBTYPE_SH7722
select PINCTRL_PFC_SH7723 if CPU_SUBTYPE_SH7723
select PINCTRL_PFC_SH7724 if CPU_SUBTYPE_SH7724
select PINCTRL_PFC_SH7734 if CPU_SUBTYPE_SH7734
select PINCTRL_PFC_SH7757 if CPU_SUBTYPE_SH7757
select PINCTRL_PFC_SH7785 if CPU_SUBTYPE_SH7785
select PINCTRL_PFC_SH7786 if CPU_SUBTYPE_SH7786
select PINCTRL_PFC_SHX3 if CPU_SUBTYPE_SHX3
help
This enables pin control drivers for SH and SH Mobile platforms
This enables pin control drivers for Renesas SuperH and ARM platforms
config PINCTRL_SH_PFC_GPIO
select GPIOLIB
select PINCTRL_SH_PFC
bool
help
This enables pin control and GPIO drivers for SH/SH Mobile platforms
config PINCTRL_SH_FUNC_GPIO
select PINCTRL_SH_PFC_GPIO
bool
help
This enables legacy function GPIOs for SH platforms
config PINCTRL_PFC_EMEV2
def_bool y
depends on ARCH_EMEV2
select PINCTRL_SH_PFC
bool "Emma Mobile AV2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A73A4
def_bool y
depends on ARCH_R8A73A4
bool "R-Mobile APE6 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7740
def_bool y
depends on ARCH_R8A7740
bool "R-Mobile A1 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7743
def_bool y
depends on ARCH_R8A7743
select PINCTRL_SH_PFC
bool "RZ/G1M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7744
def_bool y
depends on ARCH_R8A7744
select PINCTRL_SH_PFC
bool "RZ/G1N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7745
def_bool y
depends on ARCH_R8A7745
select PINCTRL_SH_PFC
bool "RZ/G1E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77470
def_bool y
depends on ARCH_R8A77470
select PINCTRL_SH_PFC
bool "RZ/G1C pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774A1
def_bool y
depends on ARCH_R8A774A1
select PINCTRL_SH_PFC
bool "RZ/G2M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774C0
def_bool y
depends on ARCH_R8A774C0
select PINCTRL_SH_PFC
bool "RZ/G2E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7778
def_bool y
depends on ARCH_R8A7778
select PINCTRL_SH_PFC
bool "R-Car M1A pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7779
def_bool y
depends on ARCH_R8A7779
select PINCTRL_SH_PFC
bool "R-Car H1 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7790
def_bool y
depends on ARCH_R8A7790
select PINCTRL_SH_PFC
bool "R-Car H2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7791
def_bool y
depends on ARCH_R8A7791
select PINCTRL_SH_PFC
bool "R-Car M2-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7792
def_bool y
depends on ARCH_R8A7792
select PINCTRL_SH_PFC
bool "R-Car V2H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7793
def_bool y
depends on ARCH_R8A7793
select PINCTRL_SH_PFC
bool "R-Car M2-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7794
def_bool y
depends on ARCH_R8A7794
select PINCTRL_SH_PFC
bool "R-Car E2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7795
def_bool y
depends on ARCH_R8A7795
select PINCTRL_SH_PFC
bool "R-Car H3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7796
def_bool y
depends on ARCH_R8A7796
select PINCTRL_SH_PFC
bool "R-Car M3-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77965
def_bool y
depends on ARCH_R8A77965
select PINCTRL_SH_PFC
bool "R-Car M3-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77970
def_bool y
depends on ARCH_R8A77970
select PINCTRL_SH_PFC
bool "R-Car V3M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77980
def_bool y
depends on ARCH_R8A77980
select PINCTRL_SH_PFC
bool "R-Car V3H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77990
def_bool y
depends on ARCH_R8A77990
select PINCTRL_SH_PFC
bool "R-Car E3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77995
def_bool y
depends on ARCH_R8A77995
select PINCTRL_SH_PFC
bool "R-Car D3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203
select PINCTRL_SH_PFC_GPIO
bool "SH7203 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7264
def_bool y
depends on CPU_SUBTYPE_SH7264
select PINCTRL_SH_PFC_GPIO
bool "SH7264 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7269
def_bool y
depends on CPU_SUBTYPE_SH7269
select PINCTRL_SH_PFC_GPIO
bool "SH7269 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH73A0
def_bool y
depends on ARCH_SH73A0
bool "SH-Mobile AG5 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7720
def_bool y
depends on CPU_SUBTYPE_SH7720
select PINCTRL_SH_PFC_GPIO
bool "SH7720 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7722
def_bool y
depends on CPU_SUBTYPE_SH7722
select PINCTRL_SH_PFC_GPIO
bool "SH7722 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7723
def_bool y
depends on CPU_SUBTYPE_SH7723
select PINCTRL_SH_PFC_GPIO
bool "SH-Mobile R2 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7724
def_bool y
depends on CPU_SUBTYPE_SH7724
select PINCTRL_SH_PFC_GPIO
bool "SH-Mobile R2R pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7734
def_bool y
depends on CPU_SUBTYPE_SH7734
select PINCTRL_SH_PFC_GPIO
bool "SH7734 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7757
def_bool y
depends on CPU_SUBTYPE_SH7757
select PINCTRL_SH_PFC_GPIO
bool "SH7757 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7785
def_bool y
depends on CPU_SUBTYPE_SH7785
select PINCTRL_SH_PFC_GPIO
bool "SH7785 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7786
def_bool y
depends on CPU_SUBTYPE_SH7786
select PINCTRL_SH_PFC_GPIO
bool "SH7786 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SHX3
def_bool y
depends on CPU_SUBTYPE_SHX3
select PINCTRL_SH_PFC_GPIO
endif
bool "SH-X3 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
drivers/pinctrl/sh-pfc/Makefile
View file @ 3846e6a0
......@@ -38,3 +38,18 @@ obj-$(CONFIG_PINCTRL_PFC_SH7757) += pfc-sh7757.o
obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o
obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o
obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
ifeq ($(CONFIG_COMPILE_TEST),y)
CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7269.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7720.o += -I$(srctree)/arch/sh/include/cpu-sh3
CFLAGS_pfc-sh7722.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7723.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7724.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7734.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7757.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7785.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7786.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-shx3.o += -I$(srctree)/arch/sh/include/cpu-sh4
endif
drivers/pinctrl/sh-pfc/core.c
View file @ 3846e6a0
......@@ -571,6 +571,13 @@ static const struct of_device_id sh_pfc_of_table[] = {
.compatible = "renesas,pfc-r8a7795",
.data = &r8a7795_pinmux_info,
},
#ifdef DEBUG
{
/* For sanity checks only (nothing matches against this) */
.compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */
.data = &r8a7795es1_pinmux_info,
},
#endif /* DEBUG */
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7796
{
......@@ -709,6 +716,128 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
#define DEV_PM_OPS NULL
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
#ifdef DEBUG
static bool is0s(const u16 *enum_ids, unsigned int n)
{
unsigned int i;
for (i = 0; i < n; i++)
if (enum_ids[i])
return false;
return true;
}
static unsigned int sh_pfc_errors;
static unsigned int sh_pfc_warnings;
static void sh_pfc_check_cfg_reg(const char *drvname,
const struct pinmux_cfg_reg *cfg_reg)
{
unsigned int i, n, rw, fw;
if (cfg_reg->field_width) {
/* Checked at build time */
return;
}
for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
drvname, cfg_reg->reg, rw, rw + fw - 1);
sh_pfc_warnings++;
}
n += 1 << fw;
rw += fw;
}
if (rw != cfg_reg->reg_width) {
pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
sh_pfc_errors++;
}
if (n != cfg_reg->nr_enum_ids) {
pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
sh_pfc_errors++;
}
}
static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
{
const struct sh_pfc_function *func;
const char *drvname = info->name;
unsigned int *refcnts;
unsigned int i, j, k;
pr_info("Checking %s\n", drvname);
/* Check groups and functions */
refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
if (!refcnts)
return;
for (i = 0; i < info->nr_functions; i++) {
func = &info->functions[i];
for (j = 0; j < func->nr_groups; j++) {
for (k = 0; k < info->nr_groups; k++) {
if (!strcmp(func->groups[j],
info->groups[k].name)) {
refcnts[k]++;
break;
}
}
if (k == info->nr_groups) {
pr_err("%s: function %s: group %s not found\n",
drvname, func->name, func->groups[j]);
sh_pfc_errors++;
}
}
}
for (i = 0; i < info->nr_groups; i++) {
if (!refcnts[i]) {
pr_err("%s: orphan group %s\n", drvname,
info->groups[i].name);
sh_pfc_errors++;
} else if (refcnts[i] > 1) {
pr_err("%s: group %s referred by %u functions\n",
drvname, info->groups[i].name, refcnts[i]);
sh_pfc_warnings++;
}
}
kfree(refcnts);
/* Check config register descriptions */
for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
}
static void sh_pfc_check_driver(const struct platform_driver *pdrv)
{
unsigned int i;
pr_warn("Checking builtin pinmux tables\n");
for (i = 0; pdrv->id_table[i].name[0]; i++)
sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
#ifdef CONFIG_OF
for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
#endif
pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
sh_pfc_warnings);
}
#else /* !DEBUG */
static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
#endif /* !DEBUG */
static int sh_pfc_probe(struct platform_device *pdev)
{
#ifdef CONFIG_OF
......@@ -840,6 +969,7 @@ static struct platform_driver sh_pfc_driver = {
static int __init sh_pfc_init(void)
{
sh_pfc_check_driver(&sh_pfc_driver);
return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);
drivers/pinctrl/sh-pfc/gpio.c
View file @ 3846e6a0
......@@ -252,7 +252,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
* Function GPIOs
*/
#ifdef CONFIG_SUPERH
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
static bool __print_once;
......@@ -292,7 +292,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
return 0;
}
#endif
#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
/* -----------------------------------------------------------------------------
* Register/unregister
......@@ -369,7 +369,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
return 0;
#ifdef CONFIG_SUPERH
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
/*
* Register the GPIO to pin mappings. As pins with GPIO ports
* must come first in the ranges, skip the pins without GPIO
......@@ -397,7 +397,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
if (IS_ERR(chip))
return PTR_ERR(chip);
#endif /* CONFIG_SUPERH */
#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
return 0;
}
drivers/pinctrl/sh-pfc/pfc-emev2.c
View file @ 3846e6a0
......@@ -1433,7 +1433,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(
0, PORT31_FN, /* PIN: J18 */
0, PORT30_FN, /* PIN: H18 */
0, PORT29_FN, /* PIN: G18 */
......@@ -1466,9 +1466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_JT_SEL, PORT2_FN, /* PIN: V9 */
0, PORT1_FN, /* PIN: U10 */
0, PORT0_FN, /* PIN: V10 */
}
))
},
{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(
FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */
FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */
FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */
......@@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCD3_R2, PORT34_FN, /* PIN: A19 */
FN_LCD3_R1, PORT33_FN, /* PIN: B20 */
FN_LCD3_R0, PORT32_FN, /* PIN: A20 */
}
))
},
{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(
FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */
FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */
FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */
......@@ -1536,9 +1536,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */
FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */
FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */
}
))
},
{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(
FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */
FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */
FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */
......@@ -1571,9 +1571,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */
FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */
FN_AB_A20, PORT96_FN, /* PIN: M21 */
}
))
},
{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(
0, 0,
FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */
FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */
......@@ -1606,11 +1606,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */
FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */
FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 2, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
2, 2),
GROUP(
/* 31 - 12 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -1624,11 +1626,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -1636,11 +1640,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -1648,11 +1654,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* 31 - 14 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -1673,11 +1680,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
/* 1 - 0 */
FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
2, 2, 2),
GROUP(
/* 31 - 10 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -1692,11 +1701,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
/* 1 - 0 */
FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -1704,7 +1715,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
}
))
},
{ },
};
......
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View file @ 3846e6a0
......@@ -2284,7 +2284,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(328, 0xe6053148),
PORTCR(329, 0xe6053149),
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
MSEL1CR_31_0, MSEL1CR_31_1,
0, 0,
0, 0,
......@@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL1CR_02_0, MSEL1CR_02_1,
MSEL1CR_01_0, MSEL1CR_01_1,
MSEL1CR_00_0, MSEL1CR_00_1,
}
))
},
{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
MSEL3CR_31_0, MSEL3CR_31_1,
0, 0,
0, 0,
......@@ -2352,9 +2352,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MSEL3CR_01_0, MSEL3CR_01_1,
MSEL3CR_00_0, MSEL3CR_00_1,
}
))
},
{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
0, 0,
MSEL4CR_30_0, MSEL4CR_30_1,
MSEL4CR_29_0, MSEL4CR_29_1,
......@@ -2387,9 +2387,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MSEL4CR_01_0, MSEL4CR_01_1,
0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
MSEL5CR_31_0, MSEL5CR_31_1,
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
......@@ -2422,9 +2422,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2457,14 +2457,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MSEL8CR_01_0, MSEL8CR_01_1,
MSEL8CR_00_0, MSEL8CR_00_1,
}
))
},
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
......@@ -2473,9 +2473,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -2484,9 +2484,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, PORT85_DATA, PORT84_DATA,
......@@ -2495,9 +2495,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
......@@ -2506,9 +2506,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -2517,9 +2517,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -2528,9 +2528,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
......@@ -2539,9 +2539,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
0, 0, 0, 0,
0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
......@@ -2550,9 +2550,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
0, 0, 0, 0,
PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
......@@ -2561,9 +2561,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, PORT308_DATA,
......@@ -2572,9 +2572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -2583,7 +2583,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, PORT329_DATA, PORT328_DATA,
PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
}
))
},
{ },
};
......
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View file @ 3846e6a0
......@@ -3436,7 +3436,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(210, 0xe60530d2), /* PORT210CR */
PORTCR(211, 0xe60530d3), /* PORT211CR */
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
MSEL1CR_31_0, MSEL1CR_31_1,
MSEL1CR_30_0, MSEL1CR_30_1,
MSEL1CR_29_0, MSEL1CR_29_1,
......@@ -3461,9 +3461,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL1CR_2_0, MSEL1CR_2_1,
0, 0,
MSEL1CR_0_0, MSEL1CR_0_1,
}
))
},
{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
......@@ -3474,9 +3474,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL3CR_6_0, MSEL3CR_6_1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
......@@ -3493,9 +3493,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
MSEL4CR_1_0, MSEL4CR_1_1,
0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
MSEL5CR_31_0, MSEL5CR_31_1,
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
......@@ -3528,13 +3528,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL5CR_2_0, MSEL5CR_2_1,
0, 0,
MSEL5CR_0_0, MSEL5CR_0_1,
}
))
},
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
......@@ -3542,9 +3542,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
},
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
......@@ -3552,9 +3552,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -3562,9 +3562,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
},
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
......@@ -3572,9 +3572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -3582,9 +3582,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
},
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
......@@ -3592,9 +3592,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
......@@ -3602,9 +3602,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
......@@ -3612,9 +3612,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -3622,9 +3622,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
},
{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
......@@ -3632,7 +3632,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ },
};
......
drivers/pinctrl/sh-pfc/pfc-r8a77470.c
View file @ 3846e6a0
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View file @ 3846e6a0
......@@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
GP_0_31_FN, FN_IP1_14_11,
GP_0_30_FN, FN_IP1_10_8,
GP_0_29_FN, FN_IP1_7_5,
......@@ -2136,9 +2136,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP0_4_2,
GP_0_2_FN, FN_PENC1,
GP_0_1_FN, FN_PENC0,
GP_0_0_FN, FN_IP0_1_0 }
GP_0_0_FN, FN_IP0_1_0 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
GP_1_31_FN, FN_IP4_6_4,
GP_1_30_FN, FN_IP4_3_1,
GP_1_29_FN, FN_IP4_0,
......@@ -2170,9 +2170,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP1_27_25,
GP_1_2_FN, FN_IP1_24,
GP_1_1_FN, FN_WE0,
GP_1_0_FN, FN_IP1_23_21 }
GP_1_0_FN, FN_IP1_23_21 ))
},
{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7,
GP_2_30_FN, FN_IP6_6_5,
GP_2_29_FN, FN_IP6_4_2,
......@@ -2204,9 +2204,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP4_12_11,
GP_2_2_FN, FN_IP4_10_9,
GP_2_1_FN, FN_IP4_8,
GP_2_0_FN, FN_IP4_7 }
GP_2_0_FN, FN_IP4_7 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
GP_3_31_FN, FN_IP8_10_9,
GP_3_30_FN, FN_IP8_8_6,
GP_3_29_FN, FN_IP8_5_3,
......@@ -2238,9 +2238,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP6_10,
GP_3_2_FN, FN_SSI_SCK34,
GP_3_1_FN, FN_IP6_9,
GP_3_0_FN, FN_IP6_8 }
GP_3_0_FN, FN_IP6_8 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2272,12 +2272,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP8_21_19,
GP_4_2_FN, FN_IP8_18_16,
GP_4_1_FN, FN_IP8_15_14,
GP_4_0_FN, FN_IP8_13_11 }
GP_4_0_FN, FN_IP8_13_11 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30 [1] */
......@@ -2328,10 +2329,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TX2_E, FN_SDA2_B, 0, 0,
/* IP0_1_0 [2] */
FN_PRESETOUT, 0, FN_PWM1, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
3, 1, 1),
GROUP(
/* IP1_31 [1] */
0, 0,
/* IP1_30 [1] */
......@@ -2371,11 +2374,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A21, FN_HSPI_CLK1_B,
/* IP1_0 [1] */
FN_A20, FN_HSPI_CS1_B,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 3, 2, 3, 3, 3, 3),
GROUP(
/* IP2_31 [1] */
FN_MLB_CLK, FN_IRQ1_A,
/* IP2_30 [1] */
......@@ -2423,11 +2427,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP2_2_0 [3] */
FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
FN_EX_CS2, 0, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
1, 1, 1, 1, 1, 3, 3, 2,
3, 3, 3, 2, 3, 3, 2) {
GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
3, 3, 2),
GROUP(
/* IP3_31 [1] */
FN_DU0_DR6, FN_LCDOUT6,
/* IP3_30 [1] */
......@@ -2465,10 +2470,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SDSELF_B, 0, 0, 0,
/* IP3_1_0 [2] */
FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
3, 3, 1),
GROUP(
/* IP4_31 [1] */
0, 0,
/* IP4_30_29 [2] */
......@@ -2507,10 +2514,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
/* IP4_0 [1] */
FN_DU0_DR7, FN_LCDOUT7,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
1, 2, 2, 2),
GROUP(
/* IP5_31 [1] */
0, 0,
......@@ -2551,11 +2560,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
/* IP5_1_0 [2] */
FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
1, 2, 1, 1, 1, 1, 2, 3, 2) {
GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
1, 1, 1, 1, 2, 3, 2),
GROUP(
/* IP6_31_30 [2] */
FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
/* IP6_29_28 [2] */
......@@ -2602,10 +2612,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP6_1_0 [2] */
FN_SSI_SCK6, FN_HSPI_RX2_A,
FN_FMCLK_B, FN_CAN1_TX_B,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
GROUP(
/* IP7_31_29 [3] */
FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
......@@ -2641,10 +2652,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD0_CD, 0, FN_TX5_A, 0,
/* IP7_1_0 [2] */
FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30 [1] */
......@@ -2681,10 +2693,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP8_2_0 [3] */
FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
0, FN_HSPI_TX1_A, FN_TX3_B, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP9_31 [1] */
0, 0,
/* IP9_30 [1] */
......@@ -2723,10 +2736,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP9_2_0 [3] */
FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
0, FN_HRTS1_B, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
3, 3, 3),
GROUP(
/* IP10_31 [1] */
0, 0,
......@@ -2772,11 +2787,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ATARD1, FN_ETH_MDC,
FN_SDA1_B, 0,
0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* SEL 31 [1] */
0, 0,
......@@ -2835,11 +2851,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
/* SEL_0 (WAIT1) [1] */
FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
}
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
GROUP(
/* SEL_31 [1] */
0, 0,
......@@ -2899,7 +2916,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C2_C, 0,
/* SEL_0 (I2C1) [1] */
FN_SEL_I2C1_A, FN_SEL_I2C1_B,
}
))
},
{ },
};
......
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View file @ 3846e6a0
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View file @ 3846e6a0
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View file @ 3846e6a0
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
View file @ 3846e6a0
......@@ -1988,7 +1988,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2020,9 +2020,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
GP_0_0_FN, FN_IP0_0 }
GP_0_0_FN, FN_IP0_0 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2054,9 +2054,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP1_8,
GP_1_2_FN, FN_IP1_7,
GP_1_1_FN, FN_IP1_6,
GP_1_0_FN, FN_IP1_5, }
GP_1_0_FN, FN_IP1_5, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_A15,
GP_2_30_FN, FN_A14,
GP_2_29_FN, FN_A13,
......@@ -2088,9 +2088,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_D3,
GP_2_2_FN, FN_D2,
GP_2_1_FN, FN_D1,
GP_2_0_FN, FN_D0 }
GP_2_0_FN, FN_D0 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2122,9 +2122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_A19,
GP_3_2_FN, FN_A18,
GP_3_1_FN, FN_A17,
GP_3_0_FN, FN_A16 }
GP_3_0_FN, FN_A16 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2156,9 +2156,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_VI0_VSYNC_N,
GP_4_2_FN, FN_VI0_HSYNC_N,
GP_4_1_FN, FN_VI0_CLKENB,
GP_4_0_FN, FN_VI0_CLK }
GP_4_0_FN, FN_VI0_CLK ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2190,9 +2190,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_VI1_VSYNC_N,
GP_5_2_FN, FN_VI1_HSYNC_N,
GP_5_1_FN, FN_VI1_CLKENB,
GP_5_0_FN, FN_VI1_CLK }
GP_5_0_FN, FN_VI1_CLK ))
},
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2224,9 +2224,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, FN_IP2_3,
GP_6_2_FN, FN_IP2_2,
GP_6_1_FN, FN_IP2_1,
GP_6_0_FN, FN_IP2_0 }
GP_6_0_FN, FN_IP2_0 ))
},
{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2258,9 +2258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_3_FN, FN_IP3_3,
GP_7_2_FN, FN_IP3_2,
GP_7_1_FN, FN_IP3_1,
GP_7_0_FN, FN_IP3_0 }
GP_7_0_FN, FN_IP3_0 ))
},
{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2292,9 +2292,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_8_3_FN, FN_IP4_3_2,
GP_8_2_FN, FN_IP4_1,
GP_8_1_FN, FN_IP4_0,
GP_8_0_FN, FN_VI4_CLK }
GP_8_0_FN, FN_VI4_CLK ))
},
{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
......@@ -2326,9 +2326,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_9_3_FN, FN_IP5_2,
GP_9_2_FN, FN_IP5_1,
GP_9_1_FN, FN_IP5_0,
GP_9_0_FN, FN_VI5_CLK }
GP_9_0_FN, FN_VI5_CLK ))
},
{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
GP_10_31_FN, FN_CAN1_RX,
GP_10_30_FN, FN_CAN1_TX,
GP_10_29_FN, FN_CAN_CLK,
......@@ -2360,9 +2360,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_10_3_FN, FN_IP6_2,
GP_10_2_FN, FN_HRTS0_N,
GP_10_1_FN, FN_IP6_1,
GP_10_0_FN, FN_IP6_0 }
GP_10_0_FN, FN_IP6_0 ))
},
{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
0, 0,
0, 0,
GP_11_29_FN, FN_AVS2,
......@@ -2394,13 +2394,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_11_3_FN, FN_IP7_6,
GP_11_2_FN, FN_IP7_5_4,
GP_11_1_FN, FN_IP7_3_2,
GP_11_0_FN, FN_IP7_1_0 }
GP_11_0_FN, FN_IP7_1_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP0_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_27_24 [4] */
......@@ -2452,13 +2453,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP0_1 [1] */
FN_DU0_DR1_DATA1, 0,
/* IP0_0 [1] */
FN_DU0_DR0_DATA0, 0 }
FN_DU0_DR0_DATA0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP1_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_27_24 [4] */
......@@ -2510,13 +2512,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP1_1 [1] */
FN_DU0_EXVSYNC_DU0_VSYNC, 0,
/* IP1_0 [1] */
FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
4, 4,
4, 3, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 3, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP2_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_27_24 [4] */
......@@ -2558,13 +2561,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP2_1 [1] */
FN_VI2_CLKENB, FN_AVB_RX_DV,
/* IP2_0 [1] */
FN_VI2_CLK, FN_AVB_RX_CLK }
FN_VI2_CLK, FN_AVB_RX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
4, 4,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP3_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_27_24 [4] */
......@@ -2604,12 +2608,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP3_1 [1] */
FN_VI3_CLKENB, FN_AVB_TXD4,
/* IP3_0 [1] */
FN_VI3_CLK, FN_AVB_TX_CLK }
FN_VI3_CLK, FN_AVB_TX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
4, 3, 1,
1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 1, 2, 1, 1) {
GROUP(4, 3, 1,
1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 1, 2, 1, 1),
GROUP(
/* IP4_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_27_25 [3] */
......@@ -2645,13 +2650,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP4_1 [1] */
FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
/* IP4_0 [1] */
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
4, 4,
4, 4,
4, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 4,
4, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP5_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_27_24 [4] */
......@@ -2685,13 +2691,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP5_1 [1] */
FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
/* IP5_0 [1] */
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
4, 4,
4, 1, 2, 1,
2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 1, 2, 1,
2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP6_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_27_24 [4] */
......@@ -2727,13 +2734,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP6_1 [1] */
FN_MSIOF0_SYNC, FN_HCTS0_N,
/* IP6_0 [1] */
FN_MSIOF0_SCK, FN_HSCK0 }
FN_MSIOF0_SCK, FN_HSCK0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
4, 4,
3, 1, 1, 1, 1, 1,
2, 2, 2, 2,
1, 1, 2, 2, 2) {
GROUP(4, 4,
3, 1, 1, 1, 1, 1,
2, 2, 2, 2,
1, 1, 2, 2, 2),
GROUP(
/* IP7_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_27_24 [4] */
......@@ -2767,7 +2775,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_3_2 [2] */
FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
/* IP7_1_0 [2] */
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
{ },
};
......
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