Commit 3b139cdb authored by David Howells's avatar David Howells

Blackfin: Rename IRQ flags handling functions

Rename h/w IRQ flags handling functions to be in line with what is expected for
the irq renaming patch.  This renames local_*_hw() to hard_local_*() using the
following perl command:

	perl -pi -e 's/local_irq_(restore|enable|disable)_hw/hard_local_irq_\1/ or s/local_irq_save_hw([_a-z]*)[(]flags[)]/flags = hard_local_irq_save\1()/' `find arch/blackfin/ -name "*.[ch]"`

and then fixing up asm/irqflags.h manually.

Additionally, arch/hard_local_save_flags() and arch/hard_local_irq_save() both
return the flags rather than passing it through the argument list.
Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
parent 5c74874b
......@@ -49,7 +49,7 @@
#define prepare_arch_switch(next) \
do { \
ipipe_schedule_notify(current, next); \
local_irq_disable_hw(); \
hard_local_irq_disable(); \
} while (0)
#define task_hijacked(p) \
......@@ -57,7 +57,7 @@ do { \
int __x__ = __ipipe_root_domain_p; \
__clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
if (__x__) \
local_irq_enable_hw(); \
hard_local_irq_enable(); \
!__x__; \
})
......@@ -167,7 +167,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
#define __ipipe_run_isr(ipd, irq) \
do { \
if (!__ipipe_pipeline_head_p(ipd)) \
local_irq_enable_hw(); \
hard_local_irq_enable(); \
if (ipd == ipipe_root_domain) { \
if (unlikely(ipipe_virtual_irq_p(irq))) { \
irq_enter(); \
......@@ -183,7 +183,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
__ipipe_run_irqtail(); \
__set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
} \
local_irq_disable_hw(); \
hard_local_irq_disable(); \
} while (0)
#define __ipipe_syscall_watched_p(p, sc) \
......
......@@ -33,191 +33,201 @@ static inline unsigned long bfin_cli(void)
return flags;
}
#ifdef CONFIG_IPIPE
#include <linux/compiler.h>
#include <linux/ipipe_base.h>
#include <linux/ipipe_trace.h>
#ifdef CONFIG_DEBUG_HWERR
# define bfin_no_irqs 0x3f
#else
# define bfin_no_irqs 0x1f
#endif
#define raw_local_irq_disable() \
do { \
ipipe_check_context(ipipe_root_domain); \
__ipipe_stall_root(); \
barrier(); \
} while (0)
#define raw_local_irq_enable() \
do { \
barrier(); \
ipipe_check_context(ipipe_root_domain); \
__ipipe_unstall_root(); \
} while (0)
#define raw_local_save_flags_ptr(x) \
do { \
*(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \
} while (0)
#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x))
#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs)
#define raw_local_irq_save_ptr(x) \
do { \
*(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \
barrier(); \
} while (0)
/*****************************************************************************/
/*
* Hard, untraced CPU interrupt flag manipulation and access.
*/
static inline void __hard_local_irq_disable(void)
{
bfin_cli();
}
#define raw_local_irq_save(x) \
do { \
ipipe_check_context(ipipe_root_domain); \
raw_local_irq_save_ptr(&(x)); \
} while (0)
static inline void __hard_local_irq_enable(void)
{
bfin_sti(bfin_irq_flags);
}
static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
static inline unsigned long hard_local_save_flags(void)
{
/*
* Merge virtual and real interrupt mask bits into a single
* 32bit word.
*/
return (real & ~(1 << 31)) | ((virt != 0) << 31);
return bfin_read_IMASK();
}
static inline int raw_demangle_irq_bits(unsigned long *x)
static inline unsigned long __hard_local_irq_save(void)
{
int virt = (*x & (1 << 31)) != 0;
*x &= ~(1L << 31);
return virt;
unsigned long flags;
flags = bfin_cli();
#ifdef CONFIG_DEBUG_HWERR
bfin_sti(0x3f);
#endif
return flags;
}
static inline void local_irq_disable_hw_notrace(void)
static inline int hard_irqs_disabled_flags(unsigned long flags)
{
bfin_cli();
return (flags & ~0x3f) == 0;
}
static inline void local_irq_enable_hw_notrace(void)
static inline int hard_irqs_disabled(void)
{
bfin_sti(bfin_irq_flags);
unsigned long flags = hard_local_save_flags();
return hard_irqs_disabled_flags(flags);
}
#define local_save_flags_hw(flags) \
do { \
(flags) = bfin_read_IMASK(); \
} while (0)
static inline void __hard_local_irq_restore(unsigned long flags)
{
if (!hard_irqs_disabled_flags(flags))
__hard_local_irq_enable();
}
#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0)
/*****************************************************************************/
/*
* Interrupt pipe handling.
*/
#ifdef CONFIG_IPIPE
#define irqs_disabled_hw() \
({ \
unsigned long flags; \
local_save_flags_hw(flags); \
irqs_disabled_flags_hw(flags); \
})
#include <linux/compiler.h>
#include <linux/ipipe_base.h>
#include <linux/ipipe_trace.h>
static inline void local_irq_save_ptr_hw(unsigned long *flags)
/*
* Interrupt pipe interface to linux/irqflags.h.
*/
static inline void arch_local_irq_disable(void)
{
*flags = bfin_cli();
#ifdef CONFIG_DEBUG_HWERR
bfin_sti(0x3f);
#endif
ipipe_check_context(ipipe_root_domain);
__ipipe_stall_root();
barrier();
}
#define local_irq_save_hw_notrace(flags) \
do { \
local_irq_save_ptr_hw(&(flags)); \
} while (0)
static inline void arch_local_irq_enable(void)
{
barrier();
ipipe_check_context(ipipe_root_domain);
__ipipe_unstall_root();
}
static inline void local_irq_restore_hw_notrace(unsigned long flags)
static inline unsigned long arch_local_save_flags(void)
{
if (!irqs_disabled_flags_hw(flags))
local_irq_enable_hw_notrace();
return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
}
#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
# define local_irq_disable_hw() \
do { \
if (!irqs_disabled_hw()) { \
local_irq_disable_hw_notrace(); \
ipipe_trace_begin(0x80000000); \
} \
} while (0)
# define local_irq_enable_hw() \
do { \
if (irqs_disabled_hw()) { \
ipipe_trace_end(0x80000000); \
local_irq_enable_hw_notrace(); \
} \
} while (0)
# define local_irq_save_hw(flags) \
do { \
local_save_flags_hw(flags); \
if (!irqs_disabled_flags_hw(flags)) { \
local_irq_disable_hw_notrace(); \
ipipe_trace_begin(0x80000001); \
} \
} while (0)
# define local_irq_restore_hw(flags) \
do { \
if (!irqs_disabled_flags_hw(flags)) { \
ipipe_trace_end(0x80000001); \
local_irq_enable_hw_notrace(); \
} \
} while (0)
#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
# define local_irq_disable_hw() local_irq_disable_hw_notrace()
# define local_irq_enable_hw() local_irq_enable_hw_notrace()
# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags)
# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags)
#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
static inline int arch_irqs_disabled_flags(unsigned long flags)
{
return flags == bfin_no_irqs;
}
#else /* CONFIG_IPIPE */
static inline void arch_local_irq_save_ptr(unsigned long *_flags)
{
x = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
barrier();
}
static inline void raw_local_irq_disable(void)
static inline unsigned long arch_local_irq_save(void)
{
bfin_cli();
ipipe_check_context(ipipe_root_domain);
return __hard_local_irq_save();
}
static inline void raw_local_irq_enable(void)
static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
{
bfin_sti(bfin_irq_flags);
/*
* Merge virtual and real interrupt mask bits into a single
* 32bit word.
*/
return (real & ~(1 << 31)) | ((virt != 0) << 31);
}
static inline unsigned long arch_local_save_flags(void)
static inline int arch_demangle_irq_bits(unsigned long *x)
{
return bfin_read_IMASK();
int virt = (*x & (1 << 31)) != 0;
*x &= ~(1L << 31);
return virt;
}
#define raw_local_save_flags(flags) do { (flags) = arch_local_save_flags(); } while (0)
/*
* Interface to various arch routines that may be traced.
*/
#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
static inline void hard_local_irq_disable(void)
{
if (!hard_irqs_disabled()) {
__hard_local_irq_disable();
ipipe_trace_begin(0x80000000);
}
}
#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0)
static inline void hard_local_irq_enable(void)
{
if (hard_irqs_disabled()) {
ipipe_trace_end(0x80000000);
__hard_local_irq_enable();
}
}
static inline unsigned long __raw_local_irq_save(void)
static inline unsigned long hard_local_irq_save(void)
{
unsigned long flags = bfin_cli();
#ifdef CONFIG_DEBUG_HWERR
bfin_sti(0x3f);
#endif
unsigned long flags = hard_local_save_flags();
if (!hard_irqs_disabled_flags(flags)) {
__hard_local_irq_disable();
ipipe_trace_begin(0x80000001);
}
return flags;
}
#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
#define local_irq_save_hw(flags) raw_local_irq_save(flags)
#define local_irq_restore_hw(flags) raw_local_irq_restore(flags)
#define local_irq_enable_hw() raw_local_irq_enable()
#define local_irq_disable_hw() raw_local_irq_disable()
#define irqs_disabled_hw() irqs_disabled()
static inline void hard_local_irq_restore(unsigned long flags)
{
if (!hard_irqs_disabled_flags(flags)) {
ipipe_trace_end(0x80000001);
__hard_local_irq_enable();
}
}
#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
# define hard_local_irq_disable() __hard_local_irq_disable()
# define hard_local_irq_enable() __hard_local_irq_enable()
# define hard_local_irq_save() __hard_local_irq_save()
# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
#else /* CONFIG_IPIPE */
/*
* Direct interface to linux/irqflags.h.
*/
#define arch_local_save_flags() hard_local_save_flags()
#define arch_local_irq_save(flags) __hard_local_irq_save()
#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
#define arch_local_irq_enable() __hard_local_irq_enable()
#define arch_local_irq_disable() __hard_local_irq_disable()
#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
#define arch_irqs_disabled() hard_irqs_disabled()
/*
* Interface to various arch routines that may be traced.
*/
#define hard_local_irq_save() __hard_local_irq_save()
#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
#define hard_local_irq_enable() __hard_local_irq_enable()
#define hard_local_irq_disable() __hard_local_irq_disable()
#endif /* !CONFIG_IPIPE */
static inline void raw_local_irq_restore(unsigned long flags)
{
if (!raw_irqs_disabled_flags(flags))
raw_local_irq_enable();
}
/*
* Raw interface to linux/irqflags.h.
*/
#define raw_local_save_flags(flags) do { (flags) = arch_local_save_flags(); } while (0)
#define raw_local_irq_save(flags) do { (flags) = arch_local_irq_save(); } while (0)
#define raw_local_irq_restore(flags) arch_local_irq_restore(flags)
#define raw_local_irq_enable() arch_local_irq_enable()
#define raw_local_irq_disable() arch_local_irq_disable()
#define raw_irqs_disabled_flags(flags) arch_irqs_disabled_flags(flags)
#define raw_irqs_disabled() arch_irqs_disabled()
#endif
......@@ -97,8 +97,8 @@ static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next
}
#ifdef CONFIG_IPIPE
#define lock_mm_switch(flags) local_irq_save_hw_cond(flags)
#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags)
#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
#else
#define lock_mm_switch(flags) do { (void)(flags); } while (0)
#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
......@@ -205,9 +205,9 @@ static inline void destroy_context(struct mm_struct *mm)
}
#define ipipe_mm_switch_protect(flags) \
local_irq_save_hw_cond(flags)
flags = hard_local_irq_save_cond()
#define ipipe_mm_switch_unprotect(flags) \
local_irq_restore_hw_cond(flags)
hard_local_irq_restore_cond(flags)
#endif
......@@ -117,7 +117,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
unsigned long tmp = 0;
unsigned long flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
switch (size) {
case 1:
......@@ -139,7 +139,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
}
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return tmp;
}
......
This diff is collapsed.
......@@ -318,7 +318,7 @@ void flush_switched_cplbs(unsigned int cpu)
nr_cplb_flush[cpu]++;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
_disable_icplb();
for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
icplb_tbl[cpu][i].data = 0;
......@@ -332,7 +332,7 @@ void flush_switched_cplbs(unsigned int cpu)
bfin_write32(DCPLB_DATA0 + i * 4, 0);
}
_enable_dcplb();
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
......@@ -348,7 +348,7 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
return;
}
local_irq_save_hw(flags);
flags = hard_local_irq_save();
current_rwx_mask[cpu] = masks;
if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
......@@ -373,5 +373,5 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
addr += PAGE_SIZE;
}
_enable_dcplb();
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
......@@ -219,10 +219,10 @@ int __ipipe_syscall_root(struct pt_regs *regs)
ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
local_irq_save_hw(flags);
flags = hard_local_irq_save();
if (!__ipipe_root_domain_p) {
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return 1;
}
......@@ -230,7 +230,7 @@ int __ipipe_syscall_root(struct pt_regs *regs)
if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0)
__ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return -ret;
}
......@@ -239,14 +239,14 @@ unsigned long ipipe_critical_enter(void (*syncfn) (void))
{
unsigned long flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
return flags;
}
void ipipe_critical_exit(unsigned long flags)
{
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
static void __ipipe_no_irqtail(void)
......@@ -279,9 +279,9 @@ int ipipe_trigger_irq(unsigned irq)
return -EINVAL;
#endif
local_irq_save_hw(flags);
flags = hard_local_irq_save();
__ipipe_handle_irq(irq, NULL);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return 1;
}
......@@ -293,7 +293,7 @@ asmlinkage void __ipipe_sync_root(void)
BUG_ON(irqs_disabled());
local_irq_save_hw(flags);
flags = hard_local_irq_save();
if (irq_tail_hook)
irq_tail_hook();
......@@ -303,7 +303,7 @@ asmlinkage void __ipipe_sync_root(void)
if (ipipe_root_cpudom_var(irqpend_himask) != 0)
__ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
void ___ipipe_sync_pipeline(unsigned long syncmask)
......@@ -344,10 +344,10 @@ void __ipipe_stall_root(void)
{
unsigned long *p, flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
__set_bit(IPIPE_STALL_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
EXPORT_SYMBOL(__ipipe_stall_root);
......@@ -356,10 +356,10 @@ unsigned long __ipipe_test_and_stall_root(void)
unsigned long *p, flags;
int x;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return x;
}
......@@ -371,10 +371,10 @@ unsigned long __ipipe_test_root(void)
unsigned long flags;
int x;
local_irq_save_hw_smp(flags);
flags = hard_local_irq_save_smp();
p = &__ipipe_root_status;
x = test_bit(IPIPE_STALL_FLAG, p);
local_irq_restore_hw_smp(flags);
hard_local_irq_restore_smp(flags);
return x;
}
......@@ -384,10 +384,10 @@ void __ipipe_lock_root(void)
{
unsigned long *p, flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
__set_bit(IPIPE_SYNCDEFER_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
EXPORT_SYMBOL(__ipipe_lock_root);
......@@ -395,9 +395,9 @@ void __ipipe_unlock_root(void)
{
unsigned long *p, flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
__clear_bit(IPIPE_SYNCDEFER_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
EXPORT_SYMBOL(__ipipe_unlock_root);
......@@ -65,11 +65,11 @@ static void default_idle(void)
#ifdef CONFIG_IPIPE
ipipe_suspend_domain();
#endif
local_irq_disable_hw();
hard_local_irq_disable();
if (!need_resched())
idle_with_irq_disabled();
local_irq_enable_hw();
hard_local_irq_enable();
}
/*
......
......@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -32,7 +32,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
......@@ -43,7 +43,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -57,7 +57,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
......@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -32,7 +32,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
......@@ -43,7 +43,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -57,7 +57,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
......@@ -15,10 +15,10 @@
static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
{ \
unsigned long flags; \
local_irq_save_hw(flags); \
flags = hard_local_irq_save(); \
bfin_write16(FIO_FLAG_##name, val); \
bfin_read_CHIPID(); \
local_irq_restore_hw(flags); \
hard_local_irq_restore(flags); \
}
BFIN_WRITE_FIO_FLAG(D)
BFIN_WRITE_FIO_FLAG(C)
......@@ -30,10 +30,10 @@ static inline u16 bfin_read_FIO_FLAG_##name(void) \
{ \
unsigned long flags; \
u16 ret; \
local_irq_save_hw(flags); \
flags = hard_local_irq_save(); \
ret = bfin_read16(FIO_FLAG_##name); \
bfin_read_CHIPID(); \
local_irq_restore_hw(flags); \
hard_local_irq_restore(flags); \
return ret; \
}
BFIN_READ_FIO_FLAG(D)
......
......@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
......@@ -29,7 +29,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
......@@ -40,7 +40,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
......@@ -51,7 +51,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
......@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
......@@ -29,7 +29,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
......@@ -40,7 +40,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
......@@ -51,7 +51,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
......@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -32,7 +32,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
......@@ -43,7 +43,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -57,7 +57,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
......@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -35,7 +35,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
......@@ -46,7 +46,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
......@@ -63,7 +63,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
......@@ -18,7 +18,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
......@@ -32,7 +32,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
......@@ -43,7 +43,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
......@@ -57,7 +57,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
......@@ -134,7 +134,7 @@ static int bfin_target(struct cpufreq_policy *poli,
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
if (cpu == CPUFREQ_CPU) {
local_irq_save_hw(flags);
flags = hard_local_irq_save();
plldiv = (bfin_read_PLL_DIV() & SSEL) |
dpm_state_table[index].csel;
bfin_write_PLL_DIV(plldiv);
......@@ -155,7 +155,7 @@ static int bfin_target(struct cpufreq_policy *poli,
loops_per_jiffy = cpufreq_scale(lpj_ref,
lpj_ref_freq, freqs.new);
}
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* TODO: just test case for cycles clock source, remove later */
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
......
......@@ -132,8 +132,8 @@ static void bfin_ack_noop(unsigned int irq)
static void bfin_core_mask_irq(unsigned int irq)
{
bfin_irq_flags &= ~(1 << irq);
if (!irqs_disabled_hw())
local_irq_enable_hw();
if (!hard_irqs_disabled())
hard_local_irq_enable();
}
static void bfin_core_unmask_irq(unsigned int irq)
......@@ -148,8 +148,8 @@ static void bfin_core_unmask_irq(unsigned int irq)
* local_irq_enable just does "STI bfin_irq_flags", so it's exactly
* what we need.
*/
if (!irqs_disabled_hw())
local_irq_enable_hw();
if (!hard_irqs_disabled())
hard_local_irq_enable();
return;
}
......@@ -158,12 +158,12 @@ static void bfin_internal_mask_irq(unsigned int irq)
unsigned long flags;
#ifdef CONFIG_BF53x
local_irq_save_hw(flags);
flags = hard_local_irq_save();
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
~(1 << SIC_SYSIRQ(irq)));
#else
unsigned mask_bank, mask_bit;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
mask_bank = SIC_SYSIRQ(irq) / 32;
mask_bit = SIC_SYSIRQ(irq) % 32;
bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
......@@ -173,7 +173,7 @@ static void bfin_internal_mask_irq(unsigned int irq)
~(1 << mask_bit));
#endif
#endif
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#ifdef CONFIG_SMP
......@@ -186,12 +186,12 @@ static void bfin_internal_unmask_irq(unsigned int irq)
unsigned long flags;
#ifdef CONFIG_BF53x
local_irq_save_hw(flags);
flags = hard_local_irq_save();
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
(1 << SIC_SYSIRQ(irq)));
#else
unsigned mask_bank, mask_bit;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
mask_bank = SIC_SYSIRQ(irq) / 32;
mask_bit = SIC_SYSIRQ(irq) % 32;
#ifdef CONFIG_SMP
......@@ -207,7 +207,7 @@ static void bfin_internal_unmask_irq(unsigned int irq)
(1 << mask_bit));
#endif
#endif
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#ifdef CONFIG_SMP
......@@ -264,7 +264,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
break;
}
local_irq_save_hw(flags);
flags = hard_local_irq_save();
if (state) {
bfin_sic_iwr[bank] |= (1 << bit);
......@@ -275,7 +275,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
vr_wakeup &= ~wakeup;
}
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return 0;
}
......
......@@ -25,7 +25,7 @@ void bfin_pm_suspend_standby_enter(void)
{
unsigned long flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
bfin_pm_standby_setup();
#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
......@@ -56,7 +56,7 @@ void bfin_pm_suspend_standby_enter(void)
bfin_write_SIC_IWR(IWR_DISABLE_ALL);
#endif
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
int bf53x_suspend_l1_mem(unsigned char *memptr)
......@@ -149,12 +149,12 @@ int bfin_pm_suspend_mem_enter(void)
wakeup |= GPWE;
#endif
local_irq_save_hw(flags);
flags = hard_local_irq_save();
ret = blackfin_dma_suspend();
if (ret) {
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
kfree(memptr);
return ret;
}
......@@ -178,7 +178,7 @@ int bfin_pm_suspend_mem_enter(void)
bfin_gpio_pm_hibernate_restore();
blackfin_dma_resume();
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
kfree(memptr);
return 0;
......
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