Commit 3b7c1237 authored by Neil Armstrong's avatar Neil Armstrong

drm/meson: Add G12A support for the DW-HDMI Glue

The Amlogic G12A embeds the same Synopsys DW-HDMI Controller,
but with :
- a "backport" of the HDR signaling registers from more recent
  DW-HDMI controllers, this will need a tweak since it's not
  normally present on this version of the DW-HDMI controller
- A direct mapping of TOP and DW-HDMI registers instead of an
  internal bus accessed using read/write registers
- Support for RX-SENSE, but not yet implemented
- Support for HDMI 2.1 Dynamic HDR, but not yet implemented
- Different registers mapping for the HDMI PHY setup

This patchs adds support for these changes while providing exact
same support as the previous GXBB, GXL & GXM SoCs.
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Tested-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-12-narmstrong@baylibre.com
parent 4deb190a
This diff is collapsed.
...@@ -21,9 +21,12 @@ ...@@ -21,9 +21,12 @@
#define __MESON_DW_HDMI_H #define __MESON_DW_HDMI_H
/* /*
* Bit 7 RW Reserved. Default 1. * Bit 15-10: RW Reserved. Default 1 starting from G12A
* Bit 6 RW Reserved. Default 1. * Bit 9 RW sw_reset_i2c starting from G12A
* Bit 5 RW Reserved. Default 1. * Bit 8 RW sw_reset_axiarb starting from G12A
* Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
* Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
* Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
* Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
* Default 1. * Default 1.
* Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
...@@ -39,12 +42,16 @@ ...@@ -39,12 +42,16 @@
#define HDMITX_TOP_SW_RESET (0x000) #define HDMITX_TOP_SW_RESET (0x000)
/* /*
* Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
* Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
* Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0.
...@@ -53,6 +60,8 @@ ...@@ -53,6 +60,8 @@
#define HDMITX_TOP_CLK_CNTL (0x001) #define HDMITX_TOP_CLK_CNTL (0x001)
/* /*
* Bit 31:28 RW rxsense_glitch_width: starting from G12A
* Bit 27:16 RW rxsense_valid_width: starting from G12A
* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0.
* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0.
*/ */
...@@ -61,6 +70,9 @@ ...@@ -61,6 +70,9 @@
/* /*
* intr_maskn: MASK_N, one bit per interrupt source. * intr_maskn: MASK_N, one bit per interrupt source.
* 1=Enable interrupt source; 0=Disable interrupt source. Default 0. * 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
* [ 7] rxsense_fall starting from G12A
* [ 6] rxsense_rise starting from G12A
* [ 5] err_i2c_timeout starting from G12A
* [ 4] hdcp22_rndnum_err * [ 4] hdcp22_rndnum_err
* [ 3] nonce_rfrsh_rise * [ 3] nonce_rfrsh_rise
* [ 2] hpd_fall_intr * [ 2] hpd_fall_intr
...@@ -73,6 +85,9 @@ ...@@ -73,6 +85,9 @@
* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
* bit, read back the interrupt status. * bit, read back the interrupt status.
* Bit 31 R IP interrupt status * Bit 31 R IP interrupt status
* Bit 7 RW rxsense_fall starting from G12A
* Bit 6 RW rxsense_rise starting from G12A
* Bit 5 RW err_i2c_timeout starting from G12A
* Bit 2 RW hpd_fall * Bit 2 RW hpd_fall
* Bit 1 RW hpd_rise * Bit 1 RW hpd_rise
* Bit 0 RW IP interrupt * Bit 0 RW IP interrupt
...@@ -80,6 +95,9 @@ ...@@ -80,6 +95,9 @@
#define HDMITX_TOP_INTR_STAT (0x004) #define HDMITX_TOP_INTR_STAT (0x004)
/* /*
* [7] rxsense_fall starting from G12A
* [6] rxsense_rise starting from G12A
* [5] err_i2c_timeout starting from G12A
* [4] hdcp22_rndnum_err * [4] hdcp22_rndnum_err
* [3] nonce_rfrsh_rise * [3] nonce_rfrsh_rise
* [2] hpd_fall * [2] hpd_fall
...@@ -91,6 +109,8 @@ ...@@ -91,6 +109,8 @@
#define HDMITX_TOP_INTR_CORE BIT(0) #define HDMITX_TOP_INTR_CORE BIT(0)
#define HDMITX_TOP_INTR_HPD_RISE BIT(1) #define HDMITX_TOP_INTR_HPD_RISE BIT(1)
#define HDMITX_TOP_INTR_HPD_FALL BIT(2) #define HDMITX_TOP_INTR_HPD_FALL BIT(2)
#define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6)
#define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7)
/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; /* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
* 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
...@@ -140,7 +160,9 @@ ...@@ -140,7 +160,9 @@
*/ */
#define HDMITX_TOP_REVOCMEM_STAT (0x00D) #define HDMITX_TOP_REVOCMEM_STAT (0x00D)
/* Bit 0 R filtered HPD status. */ /* Bit 1 R filtered RxSense status
* Bit 0 R filtered HPD status.
*/
#define HDMITX_TOP_STAT0 (0x00E) #define HDMITX_TOP_STAT0 (0x00E)
#endif /* __MESON_DW_HDMI_H */ #endif /* __MESON_DW_HDMI_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment