Skip to content

L
linux
Commit 3dd8bc0d authored by Paul Mackerras's avatar Paul Mackerras
Browse files
Options

PPC32: Add support for new IBM embedded PPC cpus. 

This adds support for 405GPR, 405LP, STBx25, NP4GS3.
parent 09bbfa65
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1949 additions and 0 deletions
arch/ppc/platforms/4xx/Makefile
View file @ 3dd8bc0d
# #
# Makefile for the PowerPC 4xx linux kernel. # Makefile for the PowerPC 4xx linux kernel.
export-objs := ibm405lp.o
obj-$(CONFIG_ASH) += ash.o obj-$(CONFIG_ASH) += ash.o
obj-$(CONFIG_BEECH) += beech.o obj-$(CONFIG_BEECH) += beech.o
obj-$(CONFIG_CEDAR) += cedar.o obj-$(CONFIG_CEDAR) += cedar.o
...@@ -17,3 +19,7 @@ obj-$(CONFIG_405GP) += ibm405gp.o ...@@ -17,3 +19,7 @@ obj-$(CONFIG_405GP) += ibm405gp.o
obj-$(CONFIG_REDWOOD_4) += ibmstb3.o obj-$(CONFIG_REDWOOD_4) += ibmstb3.o
obj-$(CONFIG_REDWOOD_5) += ibmstb4.o obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
obj-$(CONFIG_NP405H) += ibmnp405h.o obj-$(CONFIG_NP405H) += ibmnp405h.o
obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
obj-$(CONFIG_NP4GS3) += ibmnp4gs.o
obj-$(CONFIG_405LP) += ibm405lp.o
obj-$(CONFIG_405GPR) += ibm405gpr.o
arch/ppc/platforms/4xx/ibm405gpr.c 0 → 100644
View file @ 3dd8bc0d
/*
*
* Copyright 2000-2002 MontaVista Software Inc.
* Current maintainer
* Armin Kuster akuster@mvista.com
*
* Module name: ibm405gpr.c
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <asm/ocp.h>
#include "ibm405gpr.h"
struct ocp_def core_ocp[] __initdata = {
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
arch/ppc/platforms/4xx/ibm405gpr.h 0 → 100644
View file @ 3dd8bc0d
/*
* ibm405gpr.h
*
*
* Armin Kuster akuster@mvista.com
* Aug, 2002
*
*
* Copyright 2002 MontaVista Softare Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifdef __KERNEL__
#ifndef __ASM_IBM405GPR_H__
#define __ASM_IBM405GPR_H__
#include <linux/config.h>
/* ibm405.h at bottom of this file */
/* PCI
* PCI Bridge config reg definitions
* see 17-19 of manual
*/
#define PPC405_PCI_CONFIG_ADDR 0xeec00000
#define PPC405_PCI_CONFIG_DATA 0xeec00004
#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
/* setbat */
#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#define OPB_BASE_START 0x40000000
#define EBIU_BASE_START 0xF0100000
/* serial port defines */
#define RS_TABLE_SIZE 2
#define UART0_INT 0
#define UART1_INT 1
#define PCIL0_BASE 0xEF400000
#define UART0_IO_BASE 0xEF600300
#define UART1_IO_BASE 0xEF600400
#define IIC0_BASE 0xEF600500
#define OPB0_BASE 0xEF600600
#define GPIO0_BASE 0xEF600700
#define EMAC0_BASE 0xEF600800
#define BL_MAC_WOL 9 /* WOL */
#define BL_MAL_SERR 10 /* MAL SERR */
#define BL_MAL_TXDE 13 /* MAL TXDE */
#define BL_MAL_RXDE 14 /* MAL RXDE */
#define BL_MAL_TXEOB 11 /* MAL TX EOB */
#define BL_MAL_RXEOB 12 /* MAL RX EOB */
#define BL_MAC_ETH0 15 /* MAC */
#define IIC_OWN 0x55
#define IIC_CLOCK 50
#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
iomem_base: (u8 *)UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#if defined(CONFIG_UART0_TTYS0)
#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
#define SERIAL_PORT_DFNS \
STD_UART_OP(0) \
STD_UART_OP(1)
#endif
#if defined(CONFIG_UART0_TTYS1)
#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
#define SERIAL_PORT_DFNS \
STD_UART_OP(1) \
STD_UART_OP(0)
#endif
/* DCR defines */
#define DCRN_CHCR_BASE 0x0B1
#define DCRN_CHPSR_BASE 0x0B4
#define DCRN_CPMSR_BASE 0x0B8
#define DCRN_CPMFR_BASE 0x0BA
#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
#define CHR1_CETE 0x00800000 /* CPU external timer enable */
#define DCRN_CHPSR_BASE 0x0B4
#define PSR_PLL_FWD_MASK 0xC0000000
#define PSR_PLL_FDBACK_MASK 0x30000000
#define PSR_PLL_TUNING_MASK 0x0E000000
#define PSR_PLB_CPU_MASK 0x01800000
#define PSR_OPB_PLB_MASK 0x00600000
#define PSR_PCI_PLB_MASK 0x00180000
#define PSR_EB_PLB_MASK 0x00060000
#define PSR_ROM_WIDTH_MASK 0x00018000
#define PSR_ROM_LOC 0x00004000
#define PSR_PCI_ASYNC_EN 0x00001000
#define PSR_PCI_ARBIT_EN 0x00000400
#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
#define IBM_CPM_CPU 0x20000000 /* processor core */
#define IBM_CPM_DMA 0x10000000 /* DMA controller */
#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
#define IBM_CPM_DCP 0x04000000 /* CodePack */
#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
| IBM_CPM_OPB | IBM_CPM_EBC \
| IBM_CPM_SDRAM0 | IBM_CPM_PLB \
| IBM_CPM_UIC | IBM_CPM_TMRCLK)
#define DCRN_DMA0_BASE 0x100
#define DCRN_DMA1_BASE 0x108
#define DCRN_DMA2_BASE 0x110
#define DCRN_DMA3_BASE 0x118
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_DMASR_BASE 0x120
#define DCRN_EBC_BASE 0x012
#define DCRN_DCP0_BASE 0x014
#define DCRN_MAL_BASE 0x180
#define DCRN_OCM0_BASE 0x018
#define DCRN_PLB0_BASE 0x084
#define DCRN_PLLMR_BASE 0x0B0
#define DCRN_POB0_BASE 0x0A0
#define DCRN_SDRAM0_BASE 0x010
#define DCRN_UIC0_BASE 0x0C0
#define UIC0 DCRN_UIC0_BASE
#include <asm/ibm405.h>
#endif /* __ASM_IBM405GPR_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/4xx/ibm405lp.c 0 → 100644
View file @ 3dd8bc0d
/*
* arch/ppc/platforms/ibm405lp.c 405LP-specific code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Copyright (C) 2002, International Business Machines Corporation
* All Rights Reserved.
*
* Bishop Brock
* IBM Research, Austin Center for Low-Power Computing
* bcbrock@us.ibm.com
* March, 2002
*/
#include <linux/config.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/stat.h>
#include <linux/string.h>
#include <asm/delay.h>
#include <asm/hardirq.h>
#include <asm/ibm4xx.h>
#include <asm/machdep.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/uaccess.h>
#include <asm/ocp.h>
struct ocp_def core_ocp[] __initdata = {
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
#ifdef CONFIG_PM
/* Set up the 405LP clock and power management unit for aggressive power
management.
Briefly, there are 3 CPM "classes":
Class 1 - Either completely asleep or awake. The "force" state is
equivalent to the "enabled" state. Many Class 1 units are
critical system components and are never power managed.
Class 2 - Can be enabled for power management, where sleep requests are
made by the peripheral, typically after an inactivity timeout.
When sleeping, critical interfaces remain active, and
awaken the unit whenever it is targeted with a transaction.
Class 3 - Can be enabled for power management, where sleep requests are
made by the CPM. Power management for these units typically
will require intelligence in a device driver.
In the current implementation, the "force" bits are only used on Class 1
devices, and only when the associated driver has the intelligence necessary
to "unforce" the power management state. A previous scheme, which tried to
enable power management based on whether a particular driver was compiled
with the kernel, caused many problems and is never used here.
Class 2 devices with timeouts are normally initialized for the most
aggressive values. There is no power management benefit of "forcing" Class
2 devices over letting their inactivity timeouts take effect. Therefore,
after being set up here, Class 2 device drivers don't need to worry about
CPM.
No Class 3 devices are handled yet. */
void __init
ibm405lp_setup_cpm(void)
{
u32 force = 0;
u32 enable = 0;
dma0_slp_t dma0_slp;
dcp0_cfg_t dcp0_cfg;
ebc0_cfg_t ebc0_cfg;
sdram0_cfg_t sdram0_cfg;
sdram0_pmit_t sdram0_pmit;
sla0_slpmd_t sla0_slpmd;
/* Initialize the CPM state */
mtdcr(DCRN_CPMFR, force);
mtdcr(DCRN_CPMER, enable);
/* IIC - Class 3 - Not handled yet. The driver should at least be able
to force/unforce itself. */
/* CPU - class 2 - There doesn't appear to be a timeout associated with
this, and the exact function is not documented anywhere. It saves a
lot of power, though. I assume this gates core clocks when the CPU
core is asleep, and probably adds a couple of cycles of latency when
the CPU core wakes up. */
enable |= IBM_CPM_CPU;
/* DMA - class 2. Set for the minimum timeout, which is 32 cycles. */
dma0_slp.reg = mfdcr(DCRN_SLP);
dma0_slp.fields.sme = 1;
dma0_slp.fields.idu = 0;
mtdcr(DCRN_SLP, dma0_slp.reg);
enable |= IBM_CPM_DMA;
/* BRG - Class 2. Seems to crash the system when enabled in 405LP Pass
1
DCP (CodePack) - Class 2. The semantics of the sleep delay are not
documented. We'll use 32 (what the heck). */
dcp0_cfg.reg = mfdcri(DCRN_DCP0, CFG);
dcp0_cfg.fields.slen = 1;
dcp0_cfg.fields.sldy = 32;
mtdcri(DCRN_DCP0, CFG, dcp0_cfg.reg);
enable |= IBM_CPM_DCP;
/* EBC - Class 2. Set for minimum timeout, which is 32 cycles. [ I
think this is 32. It may be 64. I don't trust the documentation. ]
*/
ebc0_cfg.reg = mfdcri(DCRN_EBC0, CFG);
ebc0_cfg.fields.pme = 1;
ebc0_cfg.fields.pmt = 1;
mtdcri(DCRN_EBC0, CFG, ebc0_cfg.reg);
enable |= IBM_CPM_EBC;
/* SDRAM - Class 2. Set for the minimum 32-cycle timeout.
The documentation on this core is clear - waking a sleeping SDRAM
controller takes 2 PLB cycles, which is added to the latency of the
memory operation. If someone can prove that this is affecting
performance we can easily back this off. */
sdram0_cfg.reg = mfdcri(DCRN_SDRAM0, CFG);
sdram0_cfg.fields.pme = 1;
mtdcri(DCRN_SDRAM0, CFG, sdram0_cfg.reg);
sdram0_pmit.reg = mfdcri(DCRN_SDRAM0, PMIT);
sdram0_pmit.fields.cnt = 0;
mtdcri(DCRN_SDRAM0, PMIT, sdram0_pmit.reg);
enable |= IBM_CPM_SDRAM0;
/* PLB - Class 2. Seems to crash the system when enabled in 405LP Pass
1.
GPIO - Class 1. This unit is used for many things, and no single
driver controls all GPIO. It's best left unmanaged (it doesn't use
much power anyway). NB: 405LP Pass 1 erratum - forcing PM on GPIO
kills the TPC.
UART0 - Class 1
UART1 - Class 1
Someone should work on the serial port drivers to enable PM support
for them. Any takers?
UIC - Class 1
CPU_TMRCLK - Class 1
These system resources are never power managed. */
/* SLA - Class 2. Set for the minimum 32-cycle timeout. */
sla0_slpmd.reg = mfdcri(DCRN_SLA0, SLPMD);
sla0_slpmd.fields.slen = 1;
sla0_slpmd.fields.slcr = 0;
mtdcri(DCRN_SLA0, SLPMD, sla0_slpmd.reg);
enable |= IBM_CPM_SLA;
/* CSI - Class 1.
TPC - Class 1.
TDES - Class 1.
The drivers for these units are power-aware, and manage the device
properly. By default these units are forced off at boot. */
force |= IBM_CPM_CSI;
force |= IBM_CPM_TPC;
force |= IBM_CPM_TDES;
/* Set the CPM state */
mtdcr(DCRN_CPMFR, force);
mtdcr(DCRN_CPMER, enable);
}
#endif
/* This routine is included here because the framebuffer driver needs a way to
tell the system the Pixel clock frequency it needs, regardless of whether
run-time frequency scaling is configured. A hook and a couple of global
variables are always present and will be used by the RTVFS driver if it is
loaded.
Pixel clock setting is kind of a hack, as the frequency steps available from
the PLB/PixClk divider may be too large to guarantee that we'll hit within
the given limits. We never set the frequency above the upper bound, but due
to quantization may need to set the frequency below the lower bound. So far
it works OK for the panels we've tried.
In general, the choice of a system clock frequency should be made with
consideration of the LCD panel to be attached, to guarantee a good clock
divider for the Pixel clock regardless of frequency scaling.
Clock frequencies are in KHz. If pixclk_min or pixclk_max are zero, we set
the lowest possible frequency to conserve energy. */
int (*set_pixclk_hook) (unsigned pixclk_min, unsigned pixclk_max) = NULL;
unsigned last_pixclk_min = 0;
unsigned last_pixclk_max = 0;
EXPORT_SYMBOL(set_pixclk_hook);
EXPORT_SYMBOL(last_pixclk_min);
EXPORT_SYMBOL(last_pixclk_max);
int
ibm405lp_set_pixclk(unsigned pixclk_min, unsigned pixclk_max)
{
unsigned divider;
bd_t *bip = (bd_t *) __res;
unsigned plb_khz = bip->bi_busfreq / 1000;
cpc0_cgcr1_t cgcr1;
if (set_pixclk_hook) {
return (set_pixclk_hook) (pixclk_min, pixclk_max);
} else {
if ((pixclk_min == 0) || (pixclk_max == 0))
divider = CPC0_DIV_MAX;
else {
divider = plb_khz / pixclk_min;
if (divider == 0)
divider = 1;
if ((divider < CPC0_DIV_MAX) &&
((plb_khz / divider) > pixclk_max))
divider++;
}
cgcr1.reg = mfdcr(DCRN_CPC0_CGCR1);
cgcr1.fields.ppxl = CPC0_DIV_ENCODE(divider);
mtdcr(DCRN_CPC0_CGCR1, cgcr1.reg);
last_pixclk_min = pixclk_min;
last_pixclk_max = pixclk_max;
return 0;
}
}
arch/ppc/platforms/4xx/ibm405lp.h 0 → 100644
View file @ 3dd8bc0d
This diff is collapsed.
arch/ppc/platforms/4xx/ibmnp4gs.c 0 → 100644
View file @ 3dd8bc0d
/*
*
* Copyright 2000-2002 MontaVista Software Inc.
* Completed implementation.
* Current maintainer
* Armin Kuster akuster@mvista.com
*
* Module name: ibmnp4gs.c
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/init.h>
#include "ibmnp4gs.h"
#include <asm/ocp.h>
struct ocp_def core_ocp[] = {
{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
{PCI, PCIL0_BASE, OCP_IRQ_NA, IBM_CPM_PCI},
{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
arch/ppc/platforms/4xx/ibmnp4gs.h 0 → 100644
View file @ 3dd8bc0d
/*
* ibmnp405gs.h
*
* Armin Kuster akuster@mvista.com
*
*
* Copyright 2002 MontaVista Softare Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifdef __KERNEL__
#ifndef __ASM_IBMNP4GS_H__
#define __ASM_IBMNP4GS_H__
#include <linux/config.h>
#include <asm/ibm_ocp.h>
/* ibm405.h at bottom of this file */
/* PCI
* PCI Bridge config reg definitions
* see 17-19 of manual
*/
#define PPC405_PCI_CONFIG_ADDR 0xeec00000
#define PPC405_PCI_CONFIG_DATA 0xeec00004
#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
/* setbat */
#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
#define PCI_CONFIG_ADDR_MASK 0x7F000000
#define PCI_CONFIG_CYCLE_ENABLE 0x80000000
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
#define PCI_CONFIG_ADDR_MASK 0x7F000000
#define PCI_CONFIG_CYCLE_ENABLE 0x80000000
#define PCI_BASE_ADDRESS_MEM_CARD1 0x80000000
#define PCI_BASE_ADDRESS_MEM_CARD2 0x90000000
#define PPC405_UART0_INT 1
#define PPC_405RAINIER2_IO_PAGE ((void*)0xe8001000)
#define PPC_405RAINIER1_IO_PAGE ((void*)0xe8002000)
#define PPC405_UART0_IO_BASE 0x300 /* mostly use (rainier_io_page+0x300) */
#define RAINIER_IO_PAGE_INTERPOSER_PADDR 0xe8000000
#define RAINIER_IO_PAGE_INTERPOSER_VADDR RAINIER_IO_PAGE_INTERPOSER_PADDR
#define RAINIER_IO_PAGE_PCI_PADDR 0xeec00000
#define RAINIER_IO_PAGE_PCI_VADDR RAINIER_IO_PAGE_PCI_PADDR
/* serial port defines */
#define RS_TABLE_SIZE 1
#define UART0_INT 1
#define PCIL0_BASE 0xEF400000
#define UART0_IO_BASE PPC_405RAINIER1_IO_PAGE + PPC405_UART0_IO_BASE
#define UART_NUMS 1
#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
iomem_base: (u8 *)UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#if defined(CONFIG_UART0_TTYS0)
#define SERIAL_PORT_DFNS \
STD_UART_OP(0)
#endif
/* DCR defines */
#define DCRN_CHCR_BASE 0x0B1
#define DCRN_CHPSR_BASE 0x0B4
#define DCRN_CPMSR_BASE 0x0B8
#define DCRN_CPMFR_BASE 0x0BA
#define PSR_PLL_FWD_MASK 0xC0000000
#define PSR_PLL_FDBACK_MASK 0x30000000
#define PSR_PLL_TUNING_MASK 0x0E000000
#define PSR_PLB_CPU_MASK 0x01800000
#define PSR_OPB_PLB_MASK 0x00600000
#define PSR_PCI_PLB_MASK 0x00180000
#define PSR_EB_PLB_MASK 0x00060000
#define PSR_ROM_WIDTH_MASK 0x00018000
#define PSR_ROM_LOC 0x00004000
#define PSR_PCI_ASYNC_EN 0x00001000
#define PSR_PCI_ARBIT_EN 0x00000400
#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
#define IBM_CPM_CPU 0x20000000 /* processor core */
#define IBM_CPM_DMA 0x10000000 /* DMA controller */
#define IBM_CPM_BRG 0x08000000 /* PLB to OPB bridge */
#define IBM_CPM_DCP 0x04000000 /* CodePack */
#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
#define DFLT_IBM4xx_PM 0
#define DCRN_DMA0_BASE 0x100
#define DCRN_DMA1_BASE 0x108
#define DCRN_DMA2_BASE 0x110
#define DCRN_DMA3_BASE 0x118
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_DMASR_BASE 0x120
#define DCRN_EBC_BASE 0x012
#define DCRN_DCP0_BASE 0x014
#define DCRN_MAL_BASE 0x180
#define DCRN_OCM0_BASE 0x018
#define DCRN_PLB0_BASE 0x084
#define DCRN_PLLMR_BASE 0x0B0
#define DCRN_POB0_BASE 0x0A0
#define DCRN_SDRAM0_BASE 0x010
#define DCRN_UIC0_BASE 0x0C0
#define UIC0 DCRN_UIC0_BASE
#include <asm/ibm405.h>
#endif /* __ASM_IBMNP4GS_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/4xx/ibmstbx25.c 0 → 100644
View file @ 3dd8bc0d
/*
*
* Copyright 2000-2002 MontaVista Software Inc.
* Completed implementation.
* Current maintainer
* Armin Kuster akuster@mvista.com
*
* Module name: ibmstbx25.c
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <asm/ocp.h>
#include "ibmstbx25.h"
struct ocp_def core_ocp[] __initdata = {
{OCP_VENDOR_IBM, OCP_FUNC_PLB, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
{OCP_VENDOR_IBM, OCP_FUNC_16550, UART2_IO_BASE,UART2_INT, IBM_CPM_UART2},
{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
{OCP_VENDOR_IBM, OCP_FUNC_IDE, IDE0_BASE, IDE0_IRQ, OCP_CPM_NA},
{OCP_VENDOR_IBM, OCP_FUNC_EXT, EBIU_BASE_START, OCP_IRQ_NA,IBM_CPM_EBIU},
{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
};
arch/ppc/platforms/4xx/ibmstbx25.h 0 → 100644
View file @ 3dd8bc0d
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7