Commit 3e9a1a8b authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Chen-Yu Tsai

arm64: dts: allwinner: a64: Fix display clock register range

Register range of display clocks is 0x10000, as it can be seen from
DE2 documentation.

Fix it.
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Fixes: 2c796fc8 ("arm64: dts: allwinner: a64: add necessary device tree nodes for DE2 CCU")
[wens@csie.org: added fixes tag]
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent da180322
......@@ -264,7 +264,7 @@ bus@1000000 {
display_clocks: clock@0 {
compatible = "allwinner,sun50i-a64-de2-clk";
reg = <0x0 0x100000>;
reg = <0x0 0x10000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
......
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