Commit 3ec499c9 authored by Oded Gabbay's avatar Oded Gabbay

habanalabs: don't wait for ASIC CPU after reset

Upon reset of the ASIC, the driver would have waited for the CPU to come
out of reset before finishing the reset process. This was done for the
purpose of making the CPU available to answer FLR requests. However, when a
VM shuts down, the driver isn't removed so a reset never happens.
Therefore, remove this waiting period as we don't need it.
Reviewed-by: default avatarOmer Shpigelman <oshpigelman@habana.ai>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 57c76221
......@@ -2684,30 +2684,6 @@ static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
HW_CAP_MMU | HW_CAP_TPC_MBIST |
HW_CAP_GOLDEN | HW_CAP_TPC);
memset(goya->events_stat, 0, sizeof(goya->events_stat));
if (!hdev->pldm) {
int rc;
/* In case we are running inside VM and the VM is
* shutting down, we need to make sure CPU boot-loader
* is running before we can continue the VM shutdown.
* That is because the VM will send an FLR signal that
* we must answer
*/
dev_info(hdev->dev,
"Going to wait up to %ds for CPU boot loader\n",
GOYA_CPU_TIMEOUT_USEC / 1000 / 1000);
rc = hl_poll_timeout(
hdev,
mmPSOC_GLOBAL_CONF_WARM_REBOOT,
status,
(status == CPU_BOOT_STATUS_DRAM_RDY),
10000,
GOYA_CPU_TIMEOUT_USEC);
if (rc)
dev_err(hdev->dev,
"failed to wait for CPU boot loader\n");
}
}
int goya_suspend(struct hl_device *hdev)
......
......@@ -45,7 +45,7 @@
#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */
#define GOYA_CPU_TIMEOUT_USEC 15000000 /* 15s */
#define TPC_ENABLED_MASK 0xFF
......
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