Commit 3f93a4f2 authored by Robin Gong's avatar Robin Gong Committed by Vinod Koul

dmaengine: imx-sdma: remove BD_INTR for channel0

It is possible for an irq triggered by channel0 to be received later
after clks are disabled once firmware loaded during sdma probe. If
that happens then clearing them by writing to SDMA_H_INTR won't work
and the kernel will hang processing infinite interrupts. Actually,
don't need interrupt triggered on channel0 since it's pollling
SDMA_H_STATSTOP to know channel0 done rather than interrupt in
current code, just clear BD_INTR to disable channel0 interrupt to
avoid the above case.
This issue was brought by commit 1d069bfa ("dmaengine: imx-sdma:
ack channel 0 IRQ in the interrupt handler") which didn't take care
the above case.

Fixes: 1d069bfa ("dmaengine: imx-sdma: ack channel 0 IRQ in the interrupt handler")
Cc: stable@vger.kernel.org #5.0+
Signed-off-by: default avatarRobin Gong <yibin.gong@nxp.com>
Reported-by: default avatarSven Van Asbroeck <thesven73@gmail.com>
Tested-by: default avatarSven Van Asbroeck <thesven73@gmail.com>
Reviewed-by: default avatarMichael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 2b8066c3
...@@ -703,7 +703,7 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, ...@@ -703,7 +703,7 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
spin_lock_irqsave(&sdma->channel_0_lock, flags); spin_lock_irqsave(&sdma->channel_0_lock, flags);
bd0->mode.command = C0_SETPM; bd0->mode.command = C0_SETPM;
bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
bd0->mode.count = size / 2; bd0->mode.count = size / 2;
bd0->buffer_addr = buf_phys; bd0->buffer_addr = buf_phys;
bd0->ext_buffer_addr = address; bd0->ext_buffer_addr = address;
...@@ -1025,7 +1025,7 @@ static int sdma_load_context(struct sdma_channel *sdmac) ...@@ -1025,7 +1025,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
context->gReg[7] = sdmac->watermark_level; context->gReg[7] = sdmac->watermark_level;
bd0->mode.command = C0_SETDM; bd0->mode.command = C0_SETDM;
bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
bd0->mode.count = sizeof(*context) / 4; bd0->mode.count = sizeof(*context) / 4;
bd0->buffer_addr = sdma->context_phys; bd0->buffer_addr = sdma->context_phys;
bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment