Commit 3fb37703 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira Committed by Daniel Vetter

drm/i915: Covert ILK-IVB to choose DPLLS before disabling CRTCs

Use the infrastructure added in a previous patch to choose shared DPLLs
and calculate clocks before touching the hardware.

v2: Don't set mode_set hooks since dev_priv is kzalloc()'d (Ville)
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 797d0259
......@@ -7418,9 +7418,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
return dpll | DPLL_VCO_ENABLE;
}
static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
int x, int y,
struct drm_framebuffer *fb)
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
intel_clock_t clock, reduced_clock;
......@@ -7466,17 +7464,13 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
else
crtc->new_config->dpll_hw_state.fp1 = fp;
if (intel_crtc_to_shared_dpll(crtc))
intel_put_shared_dpll(crtc);
pll = intel_get_shared_dpll(crtc);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
pipe_name(crtc->pipe));
return -EINVAL;
}
} else
intel_put_shared_dpll(crtc);
}
if (is_lvds && has_reduced_clock && i915.powersave)
crtc->lowfreq_avail = true;
......@@ -12480,7 +12474,8 @@ static void intel_init_display(struct drm_device *dev)
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_plane_config = ironlake_get_plane_config;
dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
dev_priv->display.crtc_compute_clock =
ironlake_crtc_compute_clock;
dev_priv->display.crtc_enable = ironlake_crtc_enable;
dev_priv->display.crtc_disable = ironlake_crtc_disable;
dev_priv->display.off = ironlake_crtc_off;
......
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