Commit 42081173 authored by Sreekanth Reddy's avatar Sreekanth Reddy Committed by Martin K. Petersen

mpt3sas: Manage MSI-X vectors according to HBA device type

1. Do not enable MSI-X vectors for SAS2008 B0 controllers

2. Enable a single MSI-X vector for the following controller:

   a. SAS2004
   b. SAS2008
   c. SAS2008_1
   d. SAS2008_2
   e. SAS2008_3
   f. SAS2116_1
   g. SAS2116_2

3. Enable Combined Reply Post Queue Support (i.e. 96 MSI-X vectors)
   for Gen3 Invader/Fury C0 and above revision HBAs

4. Enable Combined Reply Post Queue Support (i.e. 96 MSI-X vectors)
   for all Intruder and Cutlass HBAs
Signed-off-by: default avatarSreekanth Reddy <Sreekanth.Reddy@avagotech.com>
Acked-by: default avatarChristoph Hellwig <hch@lst.de>
Reviewed-by: default avatarHannes Reinecke <hare@suse.de>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 45506049
...@@ -1712,6 +1712,14 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) ...@@ -1712,6 +1712,14 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
int base; int base;
u16 message_control; u16 message_control;
/* Check whether controller SAS2008 B0 controller,
* if it is SAS2008 B0 controller use IO-APIC instead of MSIX
*/
if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
return -EINVAL;
}
base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
if (!base) { if (!base) {
dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
...@@ -1720,9 +1728,19 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) ...@@ -1720,9 +1728,19 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
} }
/* get msix vector count */ /* get msix vector count */
/* NUMA_IO not supported for older controllers */
pci_read_config_word(ioc->pdev, base + 2, &message_control); if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
ioc->msix_vector_count = (message_control & 0x3FF) + 1; ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
ioc->msix_vector_count = 1;
else {
pci_read_config_word(ioc->pdev, base + 2, &message_control);
ioc->msix_vector_count = (message_control & 0x3FF) + 1;
}
dinitprintk(ioc, pr_info(MPT3SAS_FMT dinitprintk(ioc, pr_info(MPT3SAS_FMT
"msix is supported, vector_count(%d)\n", "msix is supported, vector_count(%d)\n",
ioc->name, ioc->msix_vector_count)); ioc->name, ioc->msix_vector_count));
...@@ -4979,7 +4997,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) ...@@ -4979,7 +4997,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
{ {
int r, i; int r, i;
int cpu_id, last_cpu_id = 0; int cpu_id, last_cpu_id = 0;
u8 revision;
dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
__func__)); __func__));
...@@ -4999,20 +5016,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) ...@@ -4999,20 +5016,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
goto out_free_resources; goto out_free_resources;
} }
/* Check whether the controller revision is C0 or above.
* only C0 and above revision controllers support 96 MSI-X vectors.
*/
revision = ioc->pdev->revision;
if ((ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3004 ||
ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3008 ||
ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_1 ||
ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_2 ||
ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_5 ||
ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_6) &&
(revision >= 0x02))
ioc->msix96_vector = 1;
ioc->rdpq_array_enable_assigned = 0; ioc->rdpq_array_enable_assigned = 0;
ioc->dma_mask = 0; ioc->dma_mask = 0;
r = mpt3sas_base_map_resources(ioc); r = mpt3sas_base_map_resources(ioc);
......
...@@ -142,6 +142,9 @@ ...@@ -142,6 +142,9 @@
#define MPT_TARGET_FLAGS_DELETED 0x04 #define MPT_TARGET_FLAGS_DELETED 0x04
#define MPT_TARGET_FASTPATH_IO 0x08 #define MPT_TARGET_FASTPATH_IO 0x08
#define SAS2_PCI_DEVICE_B0_REVISION (0x01)
#define SAS3_PCI_DEVICE_C0_REVISION (0x02)
/* /*
* Intel HBA branding * Intel HBA branding
*/ */
......
...@@ -7938,6 +7938,13 @@ _scsih_determine_hba_mpi_version(struct MPT3SAS_ADAPTER *ioc) { ...@@ -7938,6 +7938,13 @@ _scsih_determine_hba_mpi_version(struct MPT3SAS_ADAPTER *ioc) {
case MPI25_MFGPAGE_DEVID_SAS3108_5: case MPI25_MFGPAGE_DEVID_SAS3108_5:
case MPI25_MFGPAGE_DEVID_SAS3108_6: case MPI25_MFGPAGE_DEVID_SAS3108_6:
ioc->hba_mpi_version_belonged = MPI25_VERSION; ioc->hba_mpi_version_belonged = MPI25_VERSION;
/* Check whether the controller revision is C0 or above.
* only C0 and above revision controllers support 96 MSI-X
* vectors.
*/
if (ioc->pdev->revision >= SAS3_PCI_DEVICE_C0_REVISION)
ioc->msix96_vector = 1;
break; break;
} }
} }
......
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