Commit 4394a001 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'mvebu-dt-3.18-2' of git://git.infradead.org/linux-mvebu into next/dt

Pull "mvebu DT changes for v3.18 (round 2)" from Jason Cooper:

 - Armada XP
    - Add HW datasheet references to docs

 - Armada 370
    - Change internal registers to 0xf1000000 for Armada 370 RD board
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>

* tag 'mvebu-dt-3.18-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: switch the Armada 370 RD board to internal registers at 0xf1000000
  Documentation: arm: add hardware datasheet reference for Marvell Armada XP
parents 5a6da55f 32c741d0
......@@ -103,6 +103,10 @@ EBU Armada family
NOTE: not to be confused with the non-SMP 78xx0 SoCs
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
Functional Spec: http://www.marvell.com/embedded-processors/armada-xp/assets/ARMADA-XP-Functional-SpecDatasheet.pdf
Hardware Specs:
http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78230_OS.PDF
http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78260_OS.PDF
http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78460_OS.PDF
Core: Sheeva ARMv7 compatible
......
......@@ -9,6 +9,15 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
......@@ -30,7 +39,7 @@ memory {
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
......
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