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Commit 44ab4042 authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu into drm-next 

As previously discussed, this is my first pull request for the DCU DRM
driver along with the change in MAINTAINERS.
https://lkml.org/lkml/2016/1/7/26

The pull contains some code cleanup changes (e.g. removing all error
handling for the regmap calls) and several fixes.

* 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu:
  drm/fsl-dcu: fix register initialization
  drm/fsl-dcu: use mode flags for hsync/vsync polarity
  drm/fsl-dcu: fix alpha blending
  drm/fsl-dcu: mask all interrupts on initialization
  drm/fsl-dcu: handle initialization errors properly
  drm/fsl-dcu: avoid memory leak on errors
  drm/fsl-dcu: remove regmap return value checks
  drm/fsl-dcu: specify volatile registers
  drm: fsl-dcu: Fix no fb check bug
  MAINTAINERS: update for Freescale DCU DRM driver
parents 0041ee4d f76b9873
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MAINTAINERS
View file @ 44ab4042
...@@ -3764,7 +3764,7 @@ F: include/drm/exynos* ...@@ -3764,7 +3764,7 @@ F: include/drm/exynos*
F: include/uapi/drm/exynos* F: include/uapi/drm/exynos*
DRM DRIVERS FOR FREESCALE DCU DRM DRIVERS FOR FREESCALE DCU
M: Jianwei Wang <jianwei.wang.chn@gmail.com> M: Stefan Agner <stefan@agner.ch>
M: Alison Wang <alison.wang@freescale.com> M: Alison Wang <alison.wang@freescale.com>
L: dri-devel@lists.freedesktop.org L: dri-devel@lists.freedesktop.org
S: Supported S: Supported
......
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
View file @ 44ab4042
...@@ -42,34 +42,24 @@ static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc) ...@@ -42,34 +42,24 @@ static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
int ret;
ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
DCU_MODE_DCU_MODE_MASK, DCU_MODE_DCU_MODE_MASK,
DCU_MODE_DCU_MODE(DCU_MODE_OFF)); DCU_MODE_DCU_MODE(DCU_MODE_OFF));
if (ret) regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
dev_err(fsl_dev->dev, "Disable CRTC failed\n"); DCU_UPDATE_MODE_READREG);
ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
DCU_UPDATE_MODE_READREG);
if (ret)
dev_err(fsl_dev->dev, "Enable CRTC failed\n");
} }
static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc) static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
int ret;
ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
DCU_MODE_DCU_MODE_MASK, DCU_MODE_DCU_MODE_MASK,
DCU_MODE_DCU_MODE(DCU_MODE_NORMAL)); DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
if (ret) regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
dev_err(fsl_dev->dev, "Enable CRTC failed\n"); DCU_UPDATE_MODE_READREG);
ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
DCU_UPDATE_MODE_READREG);
if (ret)
dev_err(fsl_dev->dev, "Enable CRTC failed\n");
} }
static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc, static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc,
...@@ -84,9 +74,8 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) ...@@ -84,9 +74,8 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
struct drm_display_mode *mode = &crtc->state->mode; struct drm_display_mode *mode = &crtc->state->mode;
unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index; unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index, pol = 0;
unsigned long dcuclk; unsigned long dcuclk;
int ret;
index = drm_crtc_index(crtc); index = drm_crtc_index(crtc);
dcuclk = clk_get_rate(fsl_dev->clk); dcuclk = clk_get_rate(fsl_dev->clk);
...@@ -100,51 +89,36 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) ...@@ -100,51 +89,36 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
vfp = mode->vsync_start - mode->vdisplay; vfp = mode->vsync_start - mode->vdisplay;
vsw = mode->vsync_end - mode->vsync_start; vsw = mode->vsync_end - mode->vsync_start;
ret = regmap_write(fsl_dev->regmap, DCU_HSYN_PARA, if (mode->flags & DRM_MODE_FLAG_NHSYNC)
DCU_HSYN_PARA_BP(hbp) | pol |= DCU_SYN_POL_INV_HS_LOW;
DCU_HSYN_PARA_PW(hsw) |
DCU_HSYN_PARA_FP(hfp)); if (mode->flags & DRM_MODE_FLAG_NVSYNC)
if (ret) pol |= DCU_SYN_POL_INV_VS_LOW;
goto set_failed;
ret = regmap_write(fsl_dev->regmap, DCU_VSYN_PARA, regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
DCU_VSYN_PARA_BP(vbp) | DCU_HSYN_PARA_BP(hbp) |
DCU_VSYN_PARA_PW(vsw) | DCU_HSYN_PARA_PW(hsw) |
DCU_VSYN_PARA_FP(vfp)); DCU_HSYN_PARA_FP(hfp));
if (ret) regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
goto set_failed; DCU_VSYN_PARA_BP(vbp) |
ret = regmap_write(fsl_dev->regmap, DCU_DISP_SIZE, DCU_VSYN_PARA_PW(vsw) |
DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) | DCU_VSYN_PARA_FP(vfp));
DCU_DISP_SIZE_DELTA_X(mode->hdisplay)); regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
if (ret) DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
goto set_failed; DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
ret = regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div); regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
if (ret) regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
goto set_failed; regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
ret = regmap_write(fsl_dev->regmap, DCU_SYN_POL, DCU_BGND_G(0) | DCU_BGND_B(0));
DCU_SYN_POL_INV_VS_LOW | DCU_SYN_POL_INV_HS_LOW); regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
if (ret) DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
goto set_failed; regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
ret = regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) | DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
DCU_BGND_G(0) | DCU_BGND_B(0)); DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
if (ret) DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
goto set_failed; regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
ret = regmap_write(fsl_dev->regmap, DCU_DCU_MODE, DCU_UPDATE_MODE_READREG);
DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
if (ret)
goto set_failed;
ret = regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
if (ret)
goto set_failed;
ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
DCU_UPDATE_MODE_READREG);
if (ret)
goto set_failed;
return; return;
set_failed:
dev_err(dev->dev, "set DCU register failed\n");
} }
static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = { static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
...@@ -174,10 +148,15 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev) ...@@ -174,10 +148,15 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
int ret; int ret;
primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm); primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
if (!primary)
return -ENOMEM;
ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL, ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
&fsl_dcu_drm_crtc_funcs, NULL); &fsl_dcu_drm_crtc_funcs, NULL);
if (ret < 0) if (ret) {
primary->funcs->destroy(primary);
return ret; return ret;
}
drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs); drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
...@@ -185,26 +164,15 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev) ...@@ -185,26 +164,15 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
reg_num = LS1021A_LAYER_REG_NUM; reg_num = LS1021A_LAYER_REG_NUM;
else else
reg_num = VF610_LAYER_REG_NUM; reg_num = VF610_LAYER_REG_NUM;
for (i = 0; i <= fsl_dev->soc->total_layer; i++) { for (i = 0; i < fsl_dev->soc->total_layer; i++) {
for (j = 0; j < reg_num; j++) { for (j = 1; j <= reg_num; j++)
ret = regmap_write(fsl_dev->regmap, regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
DCU_CTRLDESCLN(i, j), 0);
if (ret)
goto init_failed;
}
} }
ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
DCU_MODE_DCU_MODE_MASK, DCU_MODE_DCU_MODE_MASK,
DCU_MODE_DCU_MODE(DCU_MODE_OFF)); DCU_MODE_DCU_MODE(DCU_MODE_OFF));
if (ret) regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
goto init_failed; DCU_UPDATE_MODE_READREG);
ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
DCU_UPDATE_MODE_READREG);
if (ret)
goto init_failed;
return 0; return 0;
init_failed:
dev_err(fsl_dev->dev, "init DCU register failed\n");
return ret;
} }
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
View file @ 44ab4042
...@@ -28,37 +28,36 @@ ...@@ -28,37 +28,36 @@
#include "fsl_dcu_drm_crtc.h" #include "fsl_dcu_drm_crtc.h"
#include "fsl_dcu_drm_drv.h" #include "fsl_dcu_drm_drv.h"
static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE)
return true;
return false;
}
static const struct regmap_config fsl_dcu_regmap_config = { static const struct regmap_config fsl_dcu_regmap_config = {
.reg_bits = 32, .reg_bits = 32,
.reg_stride = 4, .reg_stride = 4,
.val_bits = 32, .val_bits = 32,
.cache_type = REGCACHE_RBTREE, .cache_type = REGCACHE_RBTREE,
.volatile_reg = fsl_dcu_drm_is_volatile_reg,
}; };
static int fsl_dcu_drm_irq_init(struct drm_device *dev) static int fsl_dcu_drm_irq_init(struct drm_device *dev)
{ {
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
unsigned int value;
int ret; int ret;
ret = drm_irq_install(dev, fsl_dev->irq); ret = drm_irq_install(dev, fsl_dev->irq);
if (ret < 0) if (ret < 0)
dev_err(dev->dev, "failed to install IRQ handler\n"); dev_err(dev->dev, "failed to install IRQ handler\n");
ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0); regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0);
if (ret) regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
dev_err(dev->dev, "set DCU_INT_STATUS failed\n"); regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
ret = regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value); DCU_UPDATE_MODE_READREG);
if (ret)
dev_err(dev->dev, "read DCU_INT_MASK failed\n");
value &= DCU_INT_MASK_VBLANK;
ret = regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
if (ret)
dev_err(dev->dev, "set DCU_INT_MASK failed\n");
ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
DCU_UPDATE_MODE_READREG);
if (ret)
dev_err(dev->dev, "set DCU_UPDATE_MODE failed\n");
return ret; return ret;
} }
...@@ -120,18 +119,17 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg) ...@@ -120,18 +119,17 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
int ret; int ret;
ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status); ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
if (ret) if (ret) {
dev_err(dev->dev, "set DCU_INT_STATUS failed\n"); dev_err(dev->dev, "read DCU_INT_STATUS failed\n");
return IRQ_NONE;
}
if (int_status & DCU_INT_STATUS_VBLANK) if (int_status & DCU_INT_STATUS_VBLANK)
drm_handle_vblank(dev, 0); drm_handle_vblank(dev, 0);
ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0xffffffff); regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
if (ret) regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
dev_err(dev->dev, "set DCU_INT_STATUS failed\n"); DCU_UPDATE_MODE_READREG);
ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
DCU_UPDATE_MODE_READREG);
if (ret)
dev_err(dev->dev, "set DCU_UPDATE_MODE failed\n");
return IRQ_HANDLED; return IRQ_HANDLED;
} }
...@@ -140,15 +138,11 @@ static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, unsigned int pipe) ...@@ -140,15 +138,11 @@ static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, unsigned int pipe)
{ {
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
unsigned int value; unsigned int value;
int ret;
ret = regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value); regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
if (ret)
dev_err(dev->dev, "read DCU_INT_MASK failed\n");
value &= ~DCU_INT_MASK_VBLANK; value &= ~DCU_INT_MASK_VBLANK;
ret = regmap_write(fsl_dev->regmap, DCU_INT_MASK, value); regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
if (ret)
dev_err(dev->dev, "set DCU_INT_MASK failed\n");
return 0; return 0;
} }
...@@ -157,15 +151,10 @@ static void fsl_dcu_drm_disable_vblank(struct drm_device *dev, ...@@ -157,15 +151,10 @@ static void fsl_dcu_drm_disable_vblank(struct drm_device *dev,
{ {
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
unsigned int value; unsigned int value;
int ret;
ret = regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value); regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
if (ret)
dev_err(dev->dev, "read DCU_INT_MASK failed\n");
value |= DCU_INT_MASK_VBLANK; value |= DCU_INT_MASK_VBLANK;
ret = regmap_write(fsl_dev->regmap, DCU_INT_MASK, value); regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
if (ret)
dev_err(dev->dev, "set DCU_INT_MASK failed\n");
} }
static const struct file_operations fsl_dcu_drm_fops = { static const struct file_operations fsl_dcu_drm_fops = {
......
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
View file @ 44ab4042
...@@ -133,7 +133,9 @@ ...@@ -133,7 +133,9 @@
#define DCU_LAYER_RLE_EN BIT(15) #define DCU_LAYER_RLE_EN BIT(15)
#define DCU_LAYER_LUOFFS(x) ((x) << 4) #define DCU_LAYER_LUOFFS(x) ((x) << 4)
#define DCU_LAYER_BB_ON BIT(2) #define DCU_LAYER_BB_ON BIT(2)
#define DCU_LAYER_AB(x) (x) #define DCU_LAYER_AB_NONE 0
#define DCU_LAYER_AB_CHROMA_KEYING 1
#define DCU_LAYER_AB_WHOLE_FRAME 2
#define DCU_LAYER_CKMAX_R(x) ((x) << 16) #define DCU_LAYER_CKMAX_R(x) ((x) << 16)
#define DCU_LAYER_CKMAX_G(x) ((x) << 8) #define DCU_LAYER_CKMAX_G(x) ((x) << 8)
......
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
View file @ 44ab4042
...@@ -25,6 +25,8 @@ static const struct drm_mode_config_funcs fsl_dcu_drm_mode_config_funcs = { ...@@ -25,6 +25,8 @@ static const struct drm_mode_config_funcs fsl_dcu_drm_mode_config_funcs = {
int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev) int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev)
{ {
int ret;
drm_mode_config_init(fsl_dev->drm); drm_mode_config_init(fsl_dev->drm);
fsl_dev->drm->mode_config.min_width = 0; fsl_dev->drm->mode_config.min_width = 0;
...@@ -33,11 +35,25 @@ int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev) ...@@ -33,11 +35,25 @@ int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev)
fsl_dev->drm->mode_config.max_height = 2047; fsl_dev->drm->mode_config.max_height = 2047;
fsl_dev->drm->mode_config.funcs = &fsl_dcu_drm_mode_config_funcs; fsl_dev->drm->mode_config.funcs = &fsl_dcu_drm_mode_config_funcs;
drm_kms_helper_poll_init(fsl_dev->drm); ret = fsl_dcu_drm_crtc_create(fsl_dev);
fsl_dcu_drm_crtc_create(fsl_dev); if (ret)
fsl_dcu_drm_encoder_create(fsl_dev, &fsl_dev->crtc); return ret;
fsl_dcu_drm_connector_create(fsl_dev, &fsl_dev->encoder);
ret = fsl_dcu_drm_encoder_create(fsl_dev, &fsl_dev->crtc);
if (ret)
goto fail_encoder;
ret = fsl_dcu_drm_connector_create(fsl_dev, &fsl_dev->encoder);
if (ret)
goto fail_connector;
drm_mode_config_reset(fsl_dev->drm); drm_mode_config_reset(fsl_dev->drm);
drm_kms_helper_poll_init(fsl_dev->drm);
return 0; return 0;
fail_encoder:
fsl_dev->crtc.funcs->destroy(&fsl_dev->crtc);
fail_connector:
fsl_dev->encoder.funcs->destroy(&fsl_dev->encoder);
return ret;
} }
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
View file @ 44ab4042
...@@ -41,11 +41,17 @@ static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane, ...@@ -41,11 +41,17 @@ static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane,
{ {
struct drm_framebuffer *fb = state->fb; struct drm_framebuffer *fb = state->fb;
if (!state->fb || !state->crtc)
return 0;
switch (fb->pixel_format) { switch (fb->pixel_format) {
case DRM_FORMAT_RGB565: case DRM_FORMAT_RGB565:
case DRM_FORMAT_RGB888: case DRM_FORMAT_RGB888:
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_BGRA4444: case DRM_FORMAT_XRGB4444:
case DRM_FORMAT_ARGB4444:
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_ARGB1555: case DRM_FORMAT_ARGB1555:
case DRM_FORMAT_YUV422: case DRM_FORMAT_YUV422:
return 0; return 0;
...@@ -59,19 +65,15 @@ static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane, ...@@ -59,19 +65,15 @@ static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane,
{ {
struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private; struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
unsigned int value; unsigned int value;
int index, ret; int index;
index = fsl_dcu_drm_plane_index(plane); index = fsl_dcu_drm_plane_index(plane);
if (index < 0) if (index < 0)
return; return;
ret = regmap_read(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), &value); regmap_read(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), &value);
if (ret)
dev_err(fsl_dev->dev, "read DCU_INT_MASK failed\n");
value &= ~DCU_LAYER_EN; value &= ~DCU_LAYER_EN;
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), value); regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), value);
if (ret)
dev_err(fsl_dev->dev, "set DCU register failed\n");
} }
static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane, static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
...@@ -82,8 +84,8 @@ static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane, ...@@ -82,8 +84,8 @@ static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *state = plane->state; struct drm_plane_state *state = plane->state;
struct drm_framebuffer *fb = plane->state->fb; struct drm_framebuffer *fb = plane->state->fb;
struct drm_gem_cma_object *gem; struct drm_gem_cma_object *gem;
unsigned int alpha, bpp; unsigned int alpha = DCU_LAYER_AB_NONE, bpp;
int index, ret; int index;
if (!fb) if (!fb)
return; return;
...@@ -97,96 +99,74 @@ static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane, ...@@ -97,96 +99,74 @@ static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
switch (fb->pixel_format) { switch (fb->pixel_format) {
case DRM_FORMAT_RGB565: case DRM_FORMAT_RGB565:
bpp = FSL_DCU_RGB565; bpp = FSL_DCU_RGB565;
alpha = 0xff;
break; break;
case DRM_FORMAT_RGB888: case DRM_FORMAT_RGB888:
bpp = FSL_DCU_RGB888; bpp = FSL_DCU_RGB888;
alpha = 0xff;
break; break;
case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ARGB8888:
alpha = DCU_LAYER_AB_WHOLE_FRAME;
/* fall-through */
case DRM_FORMAT_XRGB8888:
bpp = FSL_DCU_ARGB8888; bpp = FSL_DCU_ARGB8888;
alpha = 0xff;
break; break;
case DRM_FORMAT_BGRA4444: case DRM_FORMAT_ARGB4444:
alpha = DCU_LAYER_AB_WHOLE_FRAME;
/* fall-through */
case DRM_FORMAT_XRGB4444:
bpp = FSL_DCU_ARGB4444; bpp = FSL_DCU_ARGB4444;
alpha = 0xff;
break; break;
case DRM_FORMAT_ARGB1555: case DRM_FORMAT_ARGB1555:
alpha = DCU_LAYER_AB_WHOLE_FRAME;
/* fall-through */
case DRM_FORMAT_XRGB1555:
bpp = FSL_DCU_ARGB1555; bpp = FSL_DCU_ARGB1555;
alpha = 0xff;
break; break;
case DRM_FORMAT_YUV422: case DRM_FORMAT_YUV422:
bpp = FSL_DCU_YUV422; bpp = FSL_DCU_YUV422;
alpha = 0xff;
break; break;
default: default:
return; return;
} }
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 1), regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 1),
DCU_LAYER_HEIGHT(state->crtc_h) | DCU_LAYER_HEIGHT(state->crtc_h) |
DCU_LAYER_WIDTH(state->crtc_w)); DCU_LAYER_WIDTH(state->crtc_w));
if (ret) regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 2),
goto set_failed; DCU_LAYER_POSY(state->crtc_y) |
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 2), DCU_LAYER_POSX(state->crtc_x));
DCU_LAYER_POSY(state->crtc_y) | regmap_write(fsl_dev->regmap,
DCU_LAYER_POSX(state->crtc_x)); DCU_CTRLDESCLN(index, 3), gem->paddr);
if (ret) regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4),
goto set_failed; DCU_LAYER_EN |
ret = regmap_write(fsl_dev->regmap, DCU_LAYER_TRANS(0xff) |
DCU_CTRLDESCLN(index, 3), gem->paddr); DCU_LAYER_BPP(bpp) |
if (ret) alpha);
goto set_failed; regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 5),
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), DCU_LAYER_CKMAX_R(0xFF) |
DCU_LAYER_EN | DCU_LAYER_CKMAX_G(0xFF) |
DCU_LAYER_TRANS(alpha) | DCU_LAYER_CKMAX_B(0xFF));
DCU_LAYER_BPP(bpp) | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 6),
DCU_LAYER_AB(0)); DCU_LAYER_CKMIN_R(0) |
if (ret) DCU_LAYER_CKMIN_G(0) |
goto set_failed; DCU_LAYER_CKMIN_B(0));
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 5), regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 7), 0);
DCU_LAYER_CKMAX_R(0xFF) | regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 8),
DCU_LAYER_CKMAX_G(0xFF) | DCU_LAYER_FG_FCOLOR(0));
DCU_LAYER_CKMAX_B(0xFF)); regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 9),
if (ret) DCU_LAYER_BG_BCOLOR(0));
goto set_failed;
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 6),
DCU_LAYER_CKMIN_R(0) |
DCU_LAYER_CKMIN_G(0) |
DCU_LAYER_CKMIN_B(0));
if (ret)
goto set_failed;
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 7), 0);
if (ret)
goto set_failed;
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 8),
DCU_LAYER_FG_FCOLOR(0));
if (ret)
goto set_failed;
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 9),
DCU_LAYER_BG_BCOLOR(0));
if (ret)
goto set_failed;
if (!strcmp(fsl_dev->soc->name, "ls1021a")) { if (!strcmp(fsl_dev->soc->name, "ls1021a")) {
ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 10), regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 10),
DCU_LAYER_POST_SKIP(0) | DCU_LAYER_POST_SKIP(0) |
DCU_LAYER_PRE_SKIP(0)); DCU_LAYER_PRE_SKIP(0));
if (ret)
goto set_failed;
} }
ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
DCU_MODE_DCU_MODE_MASK, DCU_MODE_DCU_MODE_MASK,
DCU_MODE_DCU_MODE(DCU_MODE_NORMAL)); DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
if (ret) regmap_write(fsl_dev->regmap,
goto set_failed; DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
ret = regmap_write(fsl_dev->regmap,
DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
if (ret)
goto set_failed;
return;
set_failed: return;
dev_err(fsl_dev->dev, "set DCU register failed\n");
} }
static void static void
...@@ -213,6 +193,7 @@ static const struct drm_plane_helper_funcs fsl_dcu_drm_plane_helper_funcs = { ...@@ -213,6 +193,7 @@ static const struct drm_plane_helper_funcs fsl_dcu_drm_plane_helper_funcs = {
static void fsl_dcu_drm_plane_destroy(struct drm_plane *plane) static void fsl_dcu_drm_plane_destroy(struct drm_plane *plane)
{ {
drm_plane_cleanup(plane); drm_plane_cleanup(plane);
kfree(plane);
} }
static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = { static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = {
...@@ -227,8 +208,11 @@ static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = { ...@@ -227,8 +208,11 @@ static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = {
static const u32 fsl_dcu_drm_plane_formats[] = { static const u32 fsl_dcu_drm_plane_formats[] = {
DRM_FORMAT_RGB565, DRM_FORMAT_RGB565,
DRM_FORMAT_RGB888, DRM_FORMAT_RGB888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888, DRM_FORMAT_ARGB8888,
DRM_FORMAT_XRGB4444,
DRM_FORMAT_ARGB4444, DRM_FORMAT_ARGB4444,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_ARGB1555, DRM_FORMAT_ARGB1555,
DRM_FORMAT_YUV422, DRM_FORMAT_YUV422,
}; };
......
drivers/gpu/drm/panel/panel-simple.c
View file @ 44ab4042
...@@ -1016,6 +1016,7 @@ static const struct drm_display_mode nec_nl4827hc19_05b_mode = { ...@@ -1016,6 +1016,7 @@ static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
.vsync_end = 272 + 2 + 4, .vsync_end = 272 + 2 + 4,
.vtotal = 272 + 2 + 4 + 2, .vtotal = 272 + 2 + 4 + 2,
.vrefresh = 74, .vrefresh = 74,
.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
}; };
static const struct panel_desc nec_nl4827hc19_05b = { static const struct panel_desc nec_nl4827hc19_05b = {
......
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