Commit 45ed285b authored by Paul Mundt's avatar Paul Mundt Committed by Paul Mundt

sh: speculative execution support for SH7780.

SH7780 has a speculative execution mode where it can speculatively
perform an instruction fetch for subroutine returns, this allows it
to be enabled. There are some various pitfalls associated with this
mode, so it's left as depending on CONFIG_EXPERIMENTAL and not
enabled by default.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent fc31b809
...@@ -366,6 +366,16 @@ config SH_STORE_QUEUES ...@@ -366,6 +366,16 @@ config SH_STORE_QUEUES
Selecting this option will enable an in-kernel API for manipulating Selecting this option will enable an in-kernel API for manipulating
the store queues integrated in the SH-4 processors. the store queues integrated in the SH-4 processors.
config SPECULATIVE_EXECUTION
bool "Speculative subroutine return"
depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
help
This enables support for a speculative instruction fetch for
subroutine return. There are various pitfalls associated with
this, as outlined in the SH7780 hardware manual.
If unsure, say N.
config CPU_HAS_INTEVT config CPU_HAS_INTEVT
bool bool
......
...@@ -41,6 +41,23 @@ __setup("no" __stringify(x), x##_setup); ...@@ -41,6 +41,23 @@ __setup("no" __stringify(x), x##_setup);
onchip_setup(fpu); onchip_setup(fpu);
onchip_setup(dsp); onchip_setup(dsp);
#ifdef CONFIG_SPECULATIVE_EXECUTION
#define CPUOPM 0xff2f0000
#define CPUOPM_RABD (1 << 5)
static void __init speculative_execution_init(void)
{
/* Clear RABD */
ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
/* Flush the update */
(void)ctrl_inl(CPUOPM);
ctrl_barrier();
}
#else
#define speculative_execution_init() do { } while (0)
#endif
/* /*
* Generic first-level cache init * Generic first-level cache init
*/ */
...@@ -261,4 +278,6 @@ asmlinkage void __init sh_cpu_init(void) ...@@ -261,4 +278,6 @@ asmlinkage void __init sh_cpu_init(void)
*/ */
ubc_wakeup(); ubc_wakeup();
#endif #endif
speculative_execution_init();
} }
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