drm/amd/display: Add hubp_init entry to hubp vtable

Different HW will need to init HUBP differently. For now, add a vtable
entry, and hook a NO-OP for DCN1 and DCN2.

In addition, future HW will need to access the HUBPREQ_DEBUG and
CUR_TTU_CNTL0 register for hubp_init. Add that here.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c

@@ -675,9 +675,11 @@ static struct hubp_funcs dcn20_hubp_funcs = {
 	.dmdata_status_done = hubp2_dmdata_status_done,
 	.hubp_read_state = hubp1_read_state,
 	.hubp_clear_underflow = hubp1_clear_underflow,
-	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl
+	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+	.hubp_init = hubp1_init,
 };
 
+
 bool hubp2_construct(
 	struct dcn20_hubp *hubp2,
 	struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h

@@ -62,6 +62,7 @@
 	SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
 	SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\
 	SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
+	SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\
 	SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
 	SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
 	SRI(VMID_SETTINGS_0, HUBPREQ, id)
@@ -146,6 +147,7 @@
 	uint32_t FLIP_PARAMETERS_0;\
 	uint32_t FLIP_PARAMETERS_1;\
 	uint32_t FLIP_PARAMETERS_2;\
+	uint32_t DCN_CUR1_TTU_CNTL0;\
 	uint32_t DCN_CUR1_TTU_CNTL1;\
 	uint32_t VMID_SETTINGS_0;\
 	uint32_t FLIP_PARAMETERS_3;\

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

@@ -601,6 +601,8 @@ static void dcn20_init_hw(struct dc *dc)
 		hubp->power_gated = false;
 		pipe_ctx->stream_res.opp = NULL;
 
+		hubp->funcs->hubp_init(hubp);
+
 		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
 		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
@@ -1224,7 +1226,7 @@ static void dcn20_program_all_pipe_in_tree(
 		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
 }
 
-static void dcn20_pipe_control_lock_global(
+void dcn20_pipe_control_lock_global(
 		struct dc *dc,
 		struct pipe_ctx *pipe,
 		bool lock)
@@ -1244,7 +1246,7 @@ static void dcn20_pipe_control_lock_global(
 	}
 }
 
-static void dcn20_pipe_control_lock(
+void dcn20_pipe_control_lock(
 	struct dc *dc,
 	struct pipe_ctx *pipe,
 	bool lock)

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

@@ -145,11 +145,11 @@ struct hubp_funcs {
 			uint32_t dmdata_sw_size,
 			const uint32_t *dmdata_sw_data);
 	bool (*dmdata_status_done)(struct hubp *hubp);
-	void(*hubp_enable_tripleBuffer)(
+	void (*hubp_enable_tripleBuffer)(
 		struct hubp *hubp,
 		bool enable);
 
-	bool(*hubp_is_triplebuffer_enabled)(
+	bool (*hubp_is_triplebuffer_enabled)(
 		struct hubp *hubp);
 
 	void (*hubp_set_flip_control_surface_gsl)(