Commit 48938b1e authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller

net: phy: mscc: add constants for used interrupt mask bits

Add constants for the used interrupts bits. This avoids the magic
number for MII_VSC85XX_INT_MASK_MASK.
Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5a8b7c4b
...@@ -80,10 +80,16 @@ enum rgmii_rx_clock_delay { ...@@ -80,10 +80,16 @@ enum rgmii_rx_clock_delay {
#define MSCC_PHY_EXT_PHY_CNTL_2 24 #define MSCC_PHY_EXT_PHY_CNTL_2 24
#define MII_VSC85XX_INT_MASK 25 #define MII_VSC85XX_INT_MASK 25
#define MII_VSC85XX_INT_MASK_MASK 0xa020 #define MII_VSC85XX_INT_MASK_MDINT BIT(15)
#define MII_VSC85XX_INT_MASK_WOL 0x0040 #define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13)
#define MII_VSC85XX_INT_MASK_WOL BIT(6)
#define MII_VSC85XX_INT_MASK_EXT BIT(5)
#define MII_VSC85XX_INT_STATUS 26 #define MII_VSC85XX_INT_STATUS 26
#define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \
MII_VSC85XX_INT_MASK_LINK_CHG | \
MII_VSC85XX_INT_MASK_EXT)
#define MSCC_PHY_WOL_MAC_CONTROL 27 #define MSCC_PHY_WOL_MAC_CONTROL 27
#define EDGE_RATE_CNTL_POS 5 #define EDGE_RATE_CNTL_POS 5
#define EDGE_RATE_CNTL_MASK 0x00E0 #define EDGE_RATE_CNTL_MASK 0x00E0
......
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