Commit 49225249 authored by Jon Hunter's avatar Jon Hunter Committed by Vinod Koul

dmaengine: tegra210-adma: Fix spelling

Correct spelling of 'register' in Tegra210 ADMA driver.

Fixes: ded1f3db ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips")
Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9ab59bf5
...@@ -95,7 +95,7 @@ struct tegra_adma; ...@@ -95,7 +95,7 @@ struct tegra_adma;
* @global_int_clear: Register offset of DMA global interrupt clear. * @global_int_clear: Register offset of DMA global interrupt clear.
* @ch_req_tx_shift: Register offset for AHUB transmit channel select. * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
* @ch_req_rx_shift: Register offset for AHUB receive channel select. * @ch_req_rx_shift: Register offset for AHUB receive channel select.
* @ch_base_offset: Reister offset of DMA channel registers. * @ch_base_offset: Register offset of DMA channel registers.
* @ch_fifo_ctrl: Default value for channel FIFO CTRL register. * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
* @ch_req_mask: Mask for Tx or Rx channel select. * @ch_req_mask: Mask for Tx or Rx channel select.
* @ch_req_max: Maximum number of Tx or Rx channels available. * @ch_req_max: Maximum number of Tx or Rx channels available.
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