Merge bk://bk.arm.linux.org.uk

into home.transmeta.com:/home/torvalds/v2.5/linux

arch/arm/Makefile

@@ -17,7 +17,7 @@ GZFLAGS		:=-9
 CFLAGS		:=$(CFLAGS:-O2=-Os)
 
 ifeq ($(CONFIG_FRAME_POINTER),y)
-CFLAGS		:=$(CFLAGS:-fomit-frame-pointer=-mapcs -mno-sched-prolog)
+CFLAGS		+=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
 endif
 
 ifeq ($(CONFIG_DEBUG_INFO),y)
@@ -36,7 +36,7 @@ apcs-$(CONFIG_CPU_26)		:=-mapcs-26 -mcpu=arm3
 # series of macros.
 arch-$(CONFIG_CPU_32v3)		:=-D__LINUX_ARM_ARCH__=3 -march=armv3
 arch-$(CONFIG_CPU_32v4)		:=-D__LINUX_ARM_ARCH__=4 -march=armv4
-arch-$(CONFIG_CPU_32v5)		:=-D__LINUX_ARM_ARCH__=5 -march=armv5
+arch-$(CONFIG_CPU_32v5)		:=-D__LINUX_ARM_ARCH__=5 -march=armv5te
 arch-$(CONFIG_CPU_XSCALE)	:=-D__LINUX_ARM_ARCH__=5 -march=armv4 -Wa,-mxscale #-march=armv5te
 
 # This selects how we optimise for the processor.
@@ -124,10 +124,10 @@ FASTFPE_OBJ	:=$(FASTFPE)/
 endif
 
 # If we have a machine-specific directory, then include it in the build.
+core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
 ifneq ($(MACHINE),)
 core-y				+= arch/arm/mach-$(MACHINE)/
 endif
-core-y				+= arch/arm/kernel/ arch/arm/mm/
 core-$(CONFIG_FPE_NWFPE)	+= arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)	+= $(FASTFPE_OBJ)
 

arch/arm/boot/compressed/head.S

@@ -664,5 +664,5 @@ memdump:	mov	r12, r0
 reloc_end:
 
 		.align
-		.section ".stack", "aw"
+		.section ".stack", "w"
 user_stack:	.space	4096

arch/arm/common/Makefile

+#
+# Makefile for the linux kernel.
+#
+
+export-objs := sa1111.o sa1111-pcibuf.o sa1111-pcipool.o
+
+obj-$(CONFIG_SA1111)	+= sa1111.o sa1111-pcibuf.o sa1111-pcipool.o
+
+obj-$(CONFIG_PCI_HOST_PLX90X0)	+= plx90x0.o
+obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o

arch/arm/kernel/Makefile

@@ -26,8 +26,6 @@ obj-$(CONFIG_MODULES)		+= armksyms.o module.o
 obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)		+= dma-isa.o
 obj-$(CONFIG_PCI)		+= bios32.o
-obj-$(CONFIG_PCI_HOST_PLX90X0)	+= plx90x0.o
-obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
 
 ifneq ($(MACHINE),ebsa110)
   obj-y		+= io.o

arch/arm/kernel/ecard.c

@@ -881,6 +881,90 @@ static void ecard_proc_init(void)
 		get_ecard_dev_info);
 }
 
+#define ec_set_resource(ec,nr,st,sz,flg)			\
+	do {							\
+		(ec)->resource[nr].name = ec->dev.name;		\
+		(ec)->resource[nr].start = st;			\
+		(ec)->resource[nr].end = (st) + (sz) - 1;	\
+		(ec)->resource[nr].flags = flg;			\
+	} while (0)
+
+static void __init ecard_init_resources(struct expansion_card *ec)
+{
+	unsigned long base = PODSLOT_IOC4_BASE;
+	unsigned int slot = ec->slot_no;
+	int i;
+
+	if (slot < 4) {
+		ec_set_resource(ec, ECARD_RES_MEMC,
+				PODSLOT_MEMC_BASE + (slot << 14),
+				PODSLOT_MEMC_SIZE, IORESOURCE_MEM);
+		base = PODSLOT_IOC0_BASE;
+	}
+
+#ifdef CONFIG_ARCH_RPC
+	if (slot < 8) {
+		ec_set_resource(ec, ECARD_RES_EASI,
+				PODSLOT_EASI_BASE + (slot << 24),
+				PODSLOT_EASI_SIZE, IORESOURCE_MEM);
+	}
+
+	if (slot == 8) {
+		ec_set_resource(ec, ECARD_RES_MEMC, NETSLOT_BASE,
+				NETSLOT_SIZE, IORESOURCE_MEM);
+	} else
+#endif
+
+	for (i = 0; i < ECARD_RES_IOCSYNC - ECARD_RES_IOCSLOW; i++) {
+		ec_set_resource(ec, i + ECARD_RES_IOCSLOW,
+				base + (slot << 14) + (i << 19),
+				PODSLOT_IOC_SIZE, IORESOURCE_MEM);
+	}
+
+	for (i = 0; i < ECARD_NUM_RESOURCES; i++) {
+		if (ec->resource[i].start &&
+		    request_resource(&iomem_resource, &ec->resource[i])) {
+			printk(KERN_ERR "%s: resource(s) not available\n",
+				ec->dev.bus_id);
+			ec->resource[i].end -= ec->resource[i].start;
+			ec->resource[i].start = 0;
+		}
+	}
+}
+
+static ssize_t ecard_show_irq(struct device *dev, char *buf)
+{
+	struct expansion_card *ec = ECARD_DEV(dev);
+	return sprintf(buf, "%u\n", ec->irq);
+}
+
+static DEVICE_ATTR(irq, S_IRUGO, ecard_show_irq, NULL);
+
+static ssize_t ecard_show_dma(struct device *dev, char *buf)
+{
+	struct expansion_card *ec = ECARD_DEV(dev);
+	return sprintf(buf, "%u\n", ec->dma);
+}
+
+static DEVICE_ATTR(dma, S_IRUGO, ecard_show_dma, NULL);
+
+static ssize_t ecard_show_resources(struct device *dev, char *buf)
+{
+	struct expansion_card *ec = ECARD_DEV(dev);
+	char *str = buf;
+	int i;
+
+	for (i = 0; i < ECARD_NUM_RESOURCES; i++)
+		str += sprintf(str, "%08lx %08lx %08lx\n",
+				ec->resource[i].start,
+				ec->resource[i].end,
+				ec->resource[i].flags);
+
+	return str - buf;
+}
+
+static DEVICE_ATTR(resource, S_IRUGO, ecard_show_resources, NULL);
+
 /*
  * Probe for an expansion card.
  *
@@ -949,6 +1033,16 @@ ecard_probe(int slot, card_type_t type)
 			break;
 		}
 
+	snprintf(ec->dev.bus_id, sizeof(ec->dev.bus_id), "ecard%d", slot);
+	snprintf(ec->dev.name, sizeof(ec->dev.name), "ecard %04x:%04x",
+		 ec->cid.manufacturer, ec->cid.product);
+	ec->dev.parent = NULL;
+	ec->dev.bus    = &ecard_bus_type;
+	ec->dev.dma_mask = &ec->dma_mask;
+	ec->dma_mask = (u64)0xffffffff;
+
+	ecard_init_resources(ec);
+
 	/*
 	 * hook the interrupt handlers
 	 */
@@ -974,14 +1068,10 @@ ecard_probe(int slot, card_type_t type)
 	*ecp = ec;
 	slot_to_expcard[slot] = ec;
 
-	snprintf(ec->dev.bus_id, sizeof(ec->dev.bus_id), "ecard%d", slot);
-	strcpy(ec->dev.name, "fixme!");
-	ec->dev.parent = NULL;
-	ec->dev.bus    = &ecard_bus_type;
-	ec->dev.dma_mask = &ec->dma_mask;
-	ec->dma_mask = (u64)0xffffffff;
-
 	device_register(&ec->dev);
+	device_create_file(&ec->dev, &dev_attr_dma);
+	device_create_file(&ec->dev, &dev_attr_irq);
+	device_create_file(&ec->dev, &dev_attr_resource);
 
 	return 0;
 

arch/arm/kernel/irq.c

@@ -78,7 +78,8 @@ static struct irqdesc bad_irq_desc = {
  *	disable_irq - disable an irq and wait for completion
  *	@irq: Interrupt to disable
  *
- *	Disable the selected interrupt line.  We do this lazily.
+ *	Disable the selected interrupt line.  Enables and disables
+ *	are nested.  We do this lazily.
  *
  *	This function may be called from IRQ context.
  */
@@ -88,8 +89,7 @@ void disable_irq(unsigned int irq)
 	unsigned long flags;
 
 	spin_lock_irqsave(&irq_controller_lock, flags);
-	if (!desc->depth++)
-		desc->enabled = 0;
+	desc->disable_depth++;
 	spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
 
@@ -107,24 +107,25 @@ void enable_irq(unsigned int irq)
 {
 	struct irqdesc *desc = irq_desc + irq;
 	unsigned long flags;
-	int pending = 0;
 
 	spin_lock_irqsave(&irq_controller_lock, flags);
-	if (unlikely(!desc->depth)) {
+	if (unlikely(!desc->disable_depth)) {
 		printk("enable_irq(%u) unbalanced from %p\n", irq,
 			__builtin_return_address(0));
-	} else if (!--desc->depth) {
+	} else if (!--desc->disable_depth) {
 		desc->probing = 0;
-		desc->enabled = 1;
 		desc->chip->unmask(irq);
-		pending = desc->pending;
-		desc->pending = 0;
+
 		/*
-		 * If the interrupt was waiting to be processed,
-		 * retrigger it.
+		 * If the interrupt is waiting to be processed,
+		 * try to re-run it.  We can't directly run it
+		 * from here since the caller might be in an
+		 * interrupt-protected region.
 		 */
-		if (pending)
+		if (desc->pending) {
+			desc->pending = 0;
 			desc->chip->rerun(irq);
+		}
 	}
 	spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
@@ -264,7 +265,7 @@ do_edge_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 	 * we shouldn't process the IRQ.  Instead, turn on the
 	 * hardware masks.
 	 */
-	if (unlikely(desc->running || !desc->enabled))
+	if (unlikely(desc->running || desc->disable_depth))
 		goto running;
 
 	/*
@@ -286,13 +287,13 @@ do_edge_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 		if (!action)
 			break;
 
-		if (desc->pending && desc->enabled) {
+		if (desc->pending && !desc->disable_depth) {
 			desc->pending = 0;
 			desc->chip->unmask(irq);
 		}
 
 		__do_irq(irq, action, regs);
-	} while (desc->pending && desc->enabled);
+	} while (desc->pending && !desc->disable_depth);
 
 	desc->running = 0;
 
@@ -328,7 +329,7 @@ do_level_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 	 */
 	desc->chip->ack(irq);
 
-	if (likely(desc->enabled)) {
+	if (likely(!desc->disable_depth)) {
 		kstat_cpu(cpu).irqs[irq]++;
 
 		/*
@@ -338,7 +339,7 @@ do_level_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 		if (action) {
 			__do_irq(irq, desc->action, regs);
 
-			if (likely(desc->enabled &&
+			if (likely(!desc->disable_depth &&
 				   !check_irq_lock(desc, irq, regs)))
 				desc->chip->unmask(irq);
 		}
@@ -390,14 +391,13 @@ void __set_irq_handler(unsigned int irq, irq_handler_t handle, int is_chained)
 	if (handle == do_bad_IRQ) {
 		desc->chip->mask(irq);
 		desc->chip->ack(irq);
-		desc->depth = 1;
-		desc->enabled = 0;
+		desc->disable_depth = 1;
 	}
 	desc->handle = handle;
 	if (handle != do_bad_IRQ && is_chained) {
 		desc->valid = 0;
 		desc->probe_ok = 0;
-		desc->depth = 0;
+		desc->disable_depth = 0;
 		desc->chip->unmask(irq);
 	}
 	spin_unlock_irqrestore(&irq_controller_lock, flags);
@@ -512,10 +512,9 @@ int setup_irq(unsigned int irq, struct irqaction *new)
  		desc->probing = 0;
 		desc->running = 0;
 		desc->pending = 0;
-		desc->depth = 1;
+		desc->disable_depth = 1;
 		if (!desc->noautoenable) {
-			desc->depth = 0;
-			desc->enabled = 1;
+			desc->disable_depth = 0;
 			desc->chip->unmask(irq);
 		}
 	}

arch/arm/kernel/setup.c

@@ -20,6 +20,7 @@
 #include <linux/tty.h>
 #include <linux/init.h>
 #include <linux/root_dev.h>
+#include <linux/cpu.h>
 
 #include <asm/elf.h>
 #include <asm/hardware.h>
@@ -691,6 +692,15 @@ void __init setup_arch(char **cmdline_p)
 #endif
 }
 
+static struct cpu cpu[1];
+
+static int __init topology_init(void)
+{
+	return register_cpu(cpu, 0, NULL);
+}
+
+subsys_initcall(topology_init);
+
 static const char *hwcap_str[] = {
 	"swp",
 	"half",

arch/arm/kernel/traps.c

@@ -53,7 +53,8 @@ static const char *handler[]= { "prefetch abort", "data abort", "address excepti
 void dump_backtrace_entry(unsigned long where, unsigned long from)
 {
 	printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
-	print_symbol("  %s\n", where);
+	print_symbol("  %s", where);
+	printk("\n");
 }
 
 /*

arch/arm/mach-ebsa110/Makefile

@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y			:= core.o io.o time.o
+obj-y			:= core.o io.o
 obj-m			:=
 obj-n			:=
 obj-			:=

arch/arm/mach-ebsa110/time.c

-/*
- *  linux/arch/arm/mach-ebsa110/time.c
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-
-#include <asm/io.h>
-
-#define PIT_CTRL		(PIT_BASE + 0x0d)
-#define PIT_T2			(PIT_BASE + 0x09)
-#define PIT_T1			(PIT_BASE + 0x05)
-#define PIT_T0			(PIT_BASE + 0x01)
-
-/*
- * This is the rate at which your MCLK signal toggles (in Hz)
- * This was measured on a 10 digit frequency counter sampling
- * over 1 second.
- */
-#define MCLK	47894000
-
-/*
- * This is the rate at which the PIT timers get clocked
- */
-#define CLKBY7	(MCLK / 7)
-
-/*
- * If CLKBY7 is larger than this, then we must do software
- * division of the timer interrupt.
- */
-#if CLKBY7 > 6553500
-#define DIVISOR	2
-#else
-#define DIVISOR 1
-#endif
-
-/*
- * This is the counter value
- */
-#define COUNT	((CLKBY7 + (DIVISOR * HZ / 2)) / (DIVISOR * HZ))
-
-extern unsigned long (*gettimeoffset)(void);
-
-static unsigned long divisor;
-
-/*
- * Get the time offset from the system PIT.  Note that if we have missed an
- * interrupt, then the PIT counter will roll over (ie, be negative).
- * This actually works out to be convenient.
- */
-static unsigned long ebsa110_gettimeoffset(void)
-{
-	unsigned long offset, count;
-
-	__raw_writeb(0x40, PIT_CTRL);
-	count = __raw_readb(PIT_T1);
-	count |= __raw_readb(PIT_T1) << 8;
-
-	/*
-	 * If count > COUNT, make the number negative.
-	 */
-	if (count > COUNT)
-		count |= 0xffff0000;
-
-	offset = COUNT * (DIVISOR - divisor);
-	offset -= count;
-
-	/*
-	 * `offset' is in units of timer counts.  Convert
-	 * offset to units of microseconds.
-	 */
-	offset = offset * (1000000 / HZ) / (COUNT * DIVISOR);
-
-	return offset;
-}
-
-int ebsa110_reset_timer(void)
-{
-	u32 count;
-
-	/* latch and read timer 1 */
-	__raw_writeb(0x40, PIT_CTRL);
-	count = __raw_readb(PIT_T1);
-	count |= __raw_readb(PIT_T1) << 8;
-
-	count += COUNT;
-
-	__raw_writeb(count & 0xff, PIT_T1);
-	__raw_writeb(count >> 8, PIT_T1);
-
-	if (divisor == 0)
-		divisor = DIVISOR;
-	divisor -= 1;
-	return divisor;
-}
-
-void __init ebsa110_setup_timer(void)
-{
-	/*
-	 * Timer 1, mode 2, LSB/MSB
-	 */
-	__raw_writeb(0x70, PIT_CTRL);
-	__raw_writeb(COUNT & 0xff, PIT_T1);
-	__raw_writeb(COUNT >> 8, PIT_T1);
-	divisor = DIVISOR - 1;
-
-	gettimeoffset = ebsa110_gettimeoffset;
-}

arch/arm/mach-integrator/pci_v3.c

@@ -31,6 +31,7 @@
 #include <linux/init.h>
 
 #include <asm/hardware.h>
+#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/mach/pci.h>
@@ -295,7 +296,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 		v = __raw_readw(addr);
 		break;
 
-	case 4:
+	default:
 		v = __raw_readl(addr);
 		break;
 	}

arch/arm/mach-sa1100/Kconfig

@@ -165,6 +165,13 @@ config SA1100_JORNADA720
 	  handheld computer.  See <http://www.hp.com/jornada/products/720>
 	  for details.
 
+config SA1100_HACKKIT
+	bool "HackKit Core CPU Board"
+	depends on ARCH_SA1100
+	help
+	  Say Y here to support the HackKit Core CPU Board
+	  <http://hackkit.eletztrick.de>;
+
 config SA1100_HUW_WEBPANEL
 	bool "HuW WebPanel"
 	depends on ARCH_SA1100
@@ -307,6 +314,18 @@ config SA1100_STORK
 	  Say Y here if you intend to run this kernel on the Stork
 	  handheld computer.
 
+#config SA1100_TRIZEPS
+#	bool "Trizeps"
+#	depends on ARCH_SA1100
+#	help
+#	  :: write me ::
+
+#config TRIZEPS_MFTB2
+#	bool "MFTB2"
+#	depends on SA1100_TRIZEPS
+#	help
+#	  :: write me ::
+
 config SA1100_USB
 	tristate "SA1100 USB function support"
 	depends on ARCH_SA1100

arch/arm/mach-sa1100/Makefile

@@ -9,20 +9,18 @@ obj-n :=
 obj-  :=
 led-y := leds.o
 
-export-objs := dma.o generic.o pcipool.o pm.o sa1111.o sa1111-pcibuf.o
+export-objs := dma.o generic.o pm.o
 
 # This needs to be cleaned up.  We probably need to have SA1100
 # and SA1110 config symbols.
 ifeq ($(CONFIG_CPU_FREQ),y)
 obj-$(CONFIG_SA1100_ASSABET)		+= cpu-sa1110.o
 obj-$(CONFIG_SA1100_CERF)		+= cpu-sa1110.o
+obj-$(CONFIG_SA1100_HACKKIT)		+= cpu-sa1110.o
 obj-$(CONFIG_SA1100_LART)		+= cpu-sa1100.o
 obj-$(CONFIG_SA1100_PT_SYSTEM3)		+= cpu-sa1110.o
 endif
 
-# Next, the SA1111 stuff.
-obj-$(CONFIG_SA1111)			+= sa1111.o sa1111-pcibuf.o pcipool.o
-
 # Specific board support
 obj-$(CONFIG_SA1100_ADSBITSY)		+= adsbitsy.o
 led-$(CONFIG_SA1100_ADSBITSY)		+= leds-adsbitsy.o
@@ -60,6 +58,9 @@ led-$(CONFIG_SA1100_GRAPHICSMASTER)	+= leds-graphicsmaster.o
 obj-$(CONFIG_SA1100_H3600)		+= h3600.o
 export-objs				+= h3600.o
 
+obj-$(CONFIG_SA1100_HACKKIT)		+= hackkit.o
+led-$(CONFIG_SA1100_HACKKIT)		+= leds-hackkit.o
+
 obj-$(CONFIG_SA1100_HUW_WEBPANEL)	+= huw_webpanel.o
 export-objs				+= huw_webpanel.o
 
@@ -94,6 +95,9 @@ led-$(CONFIG_SA1100_SIMPAD)		+= leds-simpad.o
 obj-$(CONFIG_SA1100_STORK)		+= stork.o
 export-objs				+= stork.o
 
+obj-$(CONFIG_SA1100_TRIZEPS)		+= trizeps.o
+export-objs				+= trizeps.o
+
 obj-$(CONFIG_SA1100_XP860)		+= xp860.o
 
 obj-$(CONFIG_SA1100_YOPY)		+= yopy.o
@@ -106,4 +110,4 @@ obj-$(CONFIG_LEDS) += $(led-y)
 #obj-$(CONFIG_SA1100_USB)		+= usb/
 
 # Miscelaneous functions
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM)			+= pm.o sleep.o

arch/arm/mach-sa1100/hackkit.c

+/*
+ * linux/arch/arm/mach-sa1100/hackkit.c
+ *
+ * Copyright (C) 2002 Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
+ *
+ * This file contains all HackKit tweaks. Based on original work from
+ * Nicolas Pitre's assabet fixes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+#include <linux/serial_core.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/serial_sa1100.h>
+
+#include "generic.h"
+
+/**********************************************************************
+ *  prototypes
+ */
+
+/* init funcs */
+static void __init get_hackkit_scr(void);
+static int __init hackkit_init(void);
+static void __init hackkit_init_irq(void);
+static void __init hackkit_map_io(void);
+
+static u_int hackkit_get_mctrl(struct uart_port *port);
+static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl);
+static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate);
+
+/**********************************************************************
+ *  global data
+ */
+
+/**********************************************************************
+ *  static data
+ */
+
+static struct map_desc hackkit_io_desc[] __initdata = {
+ /* virtual     physical    length      type */
+  { 0xe8000000, 0x00000000, 0x01000000, MT_DEVICE } /* Flash bank 0 */
+};
+
+static struct sa1100_port_fns hackkit_port_fns __initdata = {
+	.set_mctrl	= hackkit_set_mctrl,
+	.get_mctrl	= hackkit_get_mctrl,
+	.pm		= hackkit_uart_pm,
+};
+
+/**********************************************************************
+ *  Static functions
+ */
+
+static void __init hackkit_map_io(void)
+{
+	sa1100_map_io();
+	iotable_init(hackkit_io_desc, ARRAY_SIZE(hackkit_io_desc));
+
+	sa1100_register_uart_fns(&hackkit_port_fns);
+	sa1100_register_uart(0, 1);	/* com port */
+	sa1100_register_uart(1, 2);
+	sa1100_register_uart(2, 3);	/* radio module */
+
+	Ser1SDCR0 |= SDCR0_SUS;
+}
+
+static void __init hackkit_init_irq(void)
+{
+	/* none used yet */
+}
+
+/**
+ *	hackkit_uart_pm - powermgmt callback function for system 3 UART
+ *	@port: uart port structure
+ *	@state: pm state
+ *	@oldstate: old pm state
+ *
+ */
+static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
+{
+	/* TODO: switch on/off uart in powersave mode */
+}
+
+/*
+ * Note! this can be called from IRQ context.
+ * FIXME: No modem ctrl lines yet.
+ */
+static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+#if 0
+	if (port->mapbase == _Ser1UTCR0) {
+		u_int set = 0, clear = 0;
+
+		if (mctrl & TIOCM_RTS)
+			set |= PT_CTRL2_RS1_RTS;
+		else
+			clear |= PT_CTRL2_RS1_RTS;
+
+		if (mctrl & TIOCM_DTR)
+			set |= PT_CTRL2_RS1_DTR;
+		else
+			clear |= PT_CTRL2_RS1_DTR;
+
+		PTCTRL2_clear(clear);
+		PTCTRL2_set(set);
+	}
+#endif
+}
+
+static u_int hackkit_get_mctrl(struct uart_port *port)
+{
+	u_int ret = 0;
+#if 0
+	u_int irqsr = PT_IRQSR;
+
+	/* need 2 reads to read current value */
+	irqsr = PT_IRQSR;
+
+	/* TODO: check IRQ source register for modem/com
+	 status lines and set them correctly. */
+#endif
+
+	ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
+
+	return ret;
+}
+
+static int __init hackkit_init(void)
+{
+	int ret = 0;
+
+	if ( !machine_is_hackkit() ) {
+		ret = -EINVAL;
+		goto DONE;
+	}
+
+	hackkit_init_irq();
+
+	ret = 0;
+DONE:
+	return ret;
+}
+
+/**********************************************************************
+ *  Exported Functions
+ */
+
+/**********************************************************************
+ *  kernel magic macros
+ */
+arch_initcall(hackkit_init);
+
+MACHINE_START(HACKKIT, "HackKit Cpu Board")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	BOOT_PARAMS(0xc0000100)
+	MAPIO(hackkit_map_io)
+	INITIRQ(sa1100_init_irq)
+MACHINE_END

arch/arm/mach-sa1100/leds-hackkit.c

+/*
+ * linux/arch/arm/mach-sa1100/leds-hackkit.c
+ *
+ * based on leds-lart.c
+ *
+ * (C) Erik Mouw (J.A.K.Mouw@its.tudelft.nl), April 21, 2000
+ * (C) Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>, 2002
+ *
+ * The HackKit has two leds (GPIO 22/23). The red led (gpio 22) is used
+ * as cpu led, the green one is used as timer led.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include "leds.h"
+
+
+#define LED_STATE_ENABLED	1
+#define LED_STATE_CLAIMED	2
+
+static unsigned int led_state;
+static unsigned int hw_led_state;
+
+#define LED_GREEN    GPIO_GPIO23
+#define LED_RED    GPIO_GPIO22
+#define LED_MASK  (LED_RED | LED_GREEN)
+
+void hackkit_leds_event(led_event_t evt)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	switch(evt) {
+		case led_start:
+			/* pin 22/23 are outputs */
+			GPDR |= LED_MASK;
+			hw_led_state = LED_MASK;
+			led_state = LED_STATE_ENABLED;
+			break;
+
+		case led_stop:
+			led_state &= ~LED_STATE_ENABLED;
+			break;
+
+		case led_claim:
+			led_state |= LED_STATE_CLAIMED;
+			hw_led_state = LED_MASK;
+			break;
+
+		case led_release:
+			led_state &= ~LED_STATE_CLAIMED;
+			hw_led_state = LED_MASK;
+			break;
+
+#ifdef CONFIG_LEDS_TIMER
+		case led_timer:
+			if (!(led_state & LED_STATE_CLAIMED))
+				hw_led_state ^= LED_GREEN;
+			break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+		case led_idle_start:
+			/* The LART people like the LED to be off when the
+			   system is idle... */
+			if (!(led_state & LED_STATE_CLAIMED))
+				hw_led_state &= ~LED_RED;
+			break;
+
+		case led_idle_end:
+			/* ... and on if the system is not idle */
+			if (!(led_state & LED_STATE_CLAIMED))
+				hw_led_state |= LED_RED;
+			break;
+#endif
+
+		case led_red_on:
+			if (led_state & LED_STATE_CLAIMED)
+				hw_led_state &= ~LED_RED;
+			break;
+
+		case led_red_off:
+			if (led_state & LED_STATE_CLAIMED)
+				hw_led_state |= LED_RED;
+			break;
+
+		case led_green_on:
+			if (led_state & LED_STATE_CLAIMED)
+				hw_led_state &= ~LED_GREEN;
+			break;
+
+		case led_green_off:
+			if (led_state & LED_STATE_CLAIMED)
+				hw_led_state |= LED_GREEN;
+			break;
+
+		default:
+			break;
+	}
+
+	/* Now set the GPIO state, or nothing will happen at all */
+	if (led_state & LED_STATE_ENABLED) {
+		GPSR = hw_led_state;
+		GPCR = hw_led_state ^ LED_MASK;
+	}
+
+	local_irq_restore(flags);
+}

arch/arm/mach-sa1100/leds.c

@@ -29,6 +29,8 @@ sa1100_leds_init(void)
 		leds_event = flexanet_leds_event;
 	if (machine_is_graphicsclient())
 		leds_event = graphicsclient_leds_event;
+	if (machine_is_hackkit())
+		leds_event = hackkit_leds_event;
 	if (machine_is_lart())
 		leds_event = lart_leds_event;
 	if (machine_is_pfs168())

arch/arm/mach-sa1100/leds.h

@@ -5,6 +5,7 @@ extern void brutus_leds_event(led_event_t evt);
 extern void cerf_leds_event(led_event_t evt);
 extern void flexanet_leds_event(led_event_t evt);
 extern void graphicsclient_leds_event(led_event_t evt);
+extern void hackkit_leds_event(led_event_t evt);
 extern void lart_leds_event(led_event_t evt);
 extern void pfs168_leds_event(led_event_t evt);
 extern void graphicsmaster_leds_event(led_event_t evt);

arch/arm/mach-sa1100/trizeps.c

+/*
+ * linux/arch/arm/mach-sa1100/trizeps.c
+ *
+ * Authors:
+ * Andreas Hofer <ho@dsa-ac.de>,
+ * Peter Lueg <pl@dsa-ac.de>,
+ * Guennadi Liakhovetski <gl@dsa-ac.de>
+ *
+ * This file contains all Trizeps-specific tweaks.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/arch/trizeps.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/serial_sa1100.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <asm/arch/serial.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/arch/irqs.h>
+
+#include "generic.h"
+
+#undef DEBUG_TRIZEPS
+#ifdef DEBUG_TRIZEPS
+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK( x... )
+#endif
+
+static struct tri_uart_cts_data_t tri_uart_cts_data[] = {
+	{ TRIZEPS_GPIO_UART1_CTS, 0, NULL, NULL,"int. UART1 cts" },
+	{ TRIZEPS_GPIO_UART2_CTS, 0, NULL, NULL,"int. UART2 cts" },
+	{ TRIZEPS_GPIO_UART3_CTS, 0, NULL, NULL,"int. UART3 cts" }
+};
+
+static void trizeps_cts_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct tri_uart_cts_data_t * uart_data = (struct tri_uart_cts_data_t *)dev_id;
+	int cts = (!(GPLR & uart_data->cts_gpio));
+
+	/* NOTE: I suppose that we will not get any interrupts
+	   if the GPIO is not changed, so maybe
+	   the cts_prev_state can be removed ... */
+	if (cts != uart_data->cts_prev_state) {
+
+		uart_data->cts_prev_state = cts;
+		uart_handle_cts_change(uart_data->port, cts);
+		DPRINTK("(IRQ %d) changed (cts=%d) stop=%d\n",
+			irq, cts, uart_data->info->tty->hw_stopped);
+	}
+}
+
+static int
+trizeps_register_cts_intr(int gpio,
+			  int irq,
+			  struct tri_uart_cts_data_t *uart_data)
+{
+	int ret = 0;
+
+	if(irq != NO_IRQ)
+	{
+		set_irq_type(irq, IRQT_BOTHEDGE);
+
+		ret = request_irq(irq, trizeps_cts_intr,
+				  SA_INTERRUPT, uart_data->name, uart_data);
+		if (ret)
+			printk(KERN_ERR "uart_open: failed to register CTS irq (%d)\n", ret);
+	}
+	return ret;
+}
+
+static void trizeps_set_mctrl(struct uart_port *port, u_int mctrl)
+{
+	if (port->mapbase == _Ser1UTCR0)
+	{
+		/**** ttySA1  ****/
+		if (mctrl & TIOCM_RTS)
+			GPCR |= TRIZEPS_GPIO_UART1_RTS;
+		else
+			GPSR |= TRIZEPS_GPIO_UART1_RTS;
+
+		DPRINTK("2 ttySA%d Set RTS %s\n",port->line,
+			mctrl & TIOCM_RTS ? "low" : "high");
+
+	}
+	else if (port->mapbase == _Ser3UTCR0)
+	{
+		/**** ttySA0  ****/
+	}
+	else
+	{
+		/**** ttySA2  ****/
+	}
+}
+
+static u_int trizeps_get_mctrl(struct uart_port *port)
+{
+	int result = TIOCM_CD | TIOCM_DSR;
+
+	if (port->mapbase == _Ser1UTCR0)
+	{
+		if (!(GPLR & TRIZEPS_GPIO_UART1_CTS))
+			result |= TIOCM_CTS;
+	}
+	else if (port->mapbase == _Ser2UTCR0)
+	{
+		result |= TIOCM_CTS;
+	}
+	else if (port->mapbase == _Ser3UTCR0)
+	{
+		result |= TIOCM_CTS;
+	}
+	else
+	{
+		result = TIOCM_CTS;
+	}
+
+	DPRINTK(" ttySA%d %s%s%s\n",port->line,
+		result & TIOCM_CD  ? "CD "  : "",
+		result & TIOCM_CTS ? "CTS " : "",
+		result & TIOCM_DSR ? "DSR " : "");
+
+	return result;
+}
+
+static struct sa1100_port_fns trizeps_port_fns __initdata = {
+	.set_mctrl =	trizeps_set_mctrl,
+	.get_mctrl =	trizeps_get_mctrl,
+};
+
+static void trizeps_power_off(void)
+{
+	printk("trizeps power off\n");
+	mdelay(100);
+	cli();
+	/* disable internal oscillator, float CS lines */
+	PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
+	/* enable wake-up on GPIO0 (Assabet...) */
+	PWER = GFER = GRER = 1;
+	/*
+	 * set scratchpad to zero, just in case it is used as a
+	 * restart address by the bootloader.
+	 */
+	PSPR = 0;
+
+	/*
+	 *  Power off
+	 *  -> disconnect AKku
+	 */
+	TRIZEPS_BCR_set(TRIZEPS_BCR0, TRIZEPS_MFT_OFF);
+
+	/*
+	 * if power supply no Akku
+	 * -> enter sleep mode
+	 */
+	PMCR = PMCR_SF;
+}
+
+static int __init trizeps_init(void)
+{
+	if (!machine_is_trizeps())
+		return -EINVAL;
+
+	DPRINTK(" \n");
+	pm_power_off = trizeps_power_off;
+
+	// Init UART2 for IrDA
+//	PPDR |= PPC_TXD2;           // Set TXD2 as output
+	Ser2UTCR4 = UTCR4_HSE;      // enable HSE
+	Ser2HSCR0 = 0;
+	Ser2HSSR0 = HSSR0_EIF | HSSR0_TUR | HSSR0_RAB | HSSR0_FRE;
+
+	/* Init MECR */
+	MECR = 0x00060006;
+
+	/* Set up external serial IRQs */
+	GAFR &= ~(GPIO_GPIO16 | GPIO_GPIO17);  // no alternate function
+	GPDR &= ~(GPIO_GPIO16 | GPIO_GPIO17);  // Set to Input
+	set_irq_type(IRQ_GPIO16, IRQT_RISING);
+	set_irq_type(IRQ_GPIO17, IRQT_RISING);
+
+	return 0;
+}
+
+__initcall(trizeps_init);
+
+static struct map_desc trizeps_io_desc[] __initdata = {
+	/* virtual	physical	length	type */
+	{ 0xF0000000l, 0x30000000l, 0x00800000l, MT_DEVICE },
+	{ 0xF2000000l, 0x38000000l, 0x00800000l, MT_DEVICE },
+};
+
+static void __init trizeps_map_io(void)
+{
+	sa1100_map_io();
+	iotable_init(trizeps_io_desc, ARRAY_SIZE(trizeps_io_desc));
+
+	sa1100_register_uart_fns(&trizeps_port_fns);
+	sa1100_register_uart(0, 3);
+	sa1100_register_uart(1, 1);
+	sa1100_register_uart(2, 2);
+}
+
+MACHINE_START(TRIZEPS, "TRIZEPS")
+	MAINTAINER("DSA")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	MAPIO(trizeps_map_io)
+	INITIRQ(sa1100_init_irq)
+MACHINE_END

drivers/acorn/char/pcf8583.c

@@ -14,6 +14,7 @@
 #include <linux/string.h>
 #include <linux/mc146818rtc.h>
 #include <linux/init.h>
+#include <linux/errno.h>
 #include <linux/bcd.h>
 
 #include "pcf8583.h"

drivers/acorn/scsi/acornscsi.c

@@ -3110,7 +3110,8 @@ static struct ecard_driver acornscsi_driver = {
 	.remove		= __devexit_p(acornscsi_remove),
 	.id_table	= acornscsi_cids,
 	.drv = {
-		.name	= "acornscsi",
+		.devclass	= &shost_devclass,
+		.name		= "acornscsi",
 	},
 };
 

drivers/acorn/scsi/cumana_1.c

@@ -334,7 +334,8 @@ static struct ecard_driver cumanascsi1_driver = {
 	.remove		= __devexit_p(cumanascsi1_remove),
 	.id_table	= cumanascsi1_cids,
 	.drv = {
-		.name	= "cumanascsi1",
+		.devclass	= &shost_devclass,
+		.name		= "cumanascsi1",
 	},
 };
 

drivers/acorn/scsi/fas216.h

@@ -22,18 +22,18 @@
 /* FAS register definitions */
 
 /* transfer count low */
-#define REG_CTCL(x)		((x)->scsi.io_port)
-#define REG_STCL(x)		((x)->scsi.io_port)
+#define REG_CTCL		(0)
+#define REG_STCL		(0)
 
 /* transfer count medium */
-#define REG_CTCM(x)		((x)->scsi.io_port + (1 << (x)->scsi.io_shift))
-#define REG_STCM(x)		((x)->scsi.io_port + (1 << (x)->scsi.io_shift))
+#define REG_CTCM		(1)
+#define REG_STCM		(1)
 
 /* fifo data */
-#define REG_FF(x)		((x)->scsi.io_port + (2 << (x)->scsi.io_shift))
+#define REG_FF			(2)
 
 /* command */
-#define REG_CMD(x)		((x)->scsi.io_port + (3 << (x)->scsi.io_shift))
+#define REG_CMD			(3)
 #define CMD_NOP			0x00
 #define CMD_FLUSHFIFO		0x01
 #define CMD_RESETCHIP		0x02
@@ -57,7 +57,7 @@
 #define CMD_WITHDMA		0x80
 
 /* status register (read) */
-#define REG_STAT(x)		((x)->scsi.io_port + (4 << (x)->scsi.io_shift))
+#define REG_STAT		(4)
 #define STAT_IO			(1 << 0)			/* IO phase		*/
 #define STAT_CD			(1 << 1)			/* CD phase		*/
 #define STAT_MSG		(1 << 2)			/* MSG phase		*/
@@ -76,11 +76,11 @@
 #define STAT_MESGIN		(STAT_MSG|STAT_CD|STAT_IO)	/* Message In		*/
 
 /* bus ID for select / reselect */
-#define REG_SDID(x)		((x)->scsi.io_port + (4 << (x)->scsi.io_shift))
+#define REG_SDID		(4)
 #define BUSID(target)		((target) & 7)
 
 /* Interrupt status register (read) */
-#define REG_INST(x)		((x)->scsi.io_port + (5 << (x)->scsi.io_shift))
+#define REG_INST		(5)
 #define INST_SELWOATN		(1 << 0)			/* Select w/o ATN	*/
 #define INST_SELATN		(1 << 1)			/* Select w/ATN		*/
 #define INST_RESELECTED		(1 << 2)			/* Reselected		*/
@@ -91,10 +91,10 @@
 #define INST_BUSRESET		(1 << 7)			/* SCSI Bus reset	*/
 
 /* Timeout register (write) */
-#define REG_STIM(x)		((x)->scsi.io_port + (5 << (x)->scsi.io_shift))
+#define REG_STIM		(5)
 
 /* Sequence step register (read) */
-#define REG_IS(x)		((x)->scsi.io_port + (6 << (x)->scsi.io_shift))
+#define REG_IS			(6)
 #define IS_BITS			0x07
 #define IS_SELARB		0x00				/* Select & Arb ok	*/
 #define IS_MSGBYTESENT		0x01				/* One byte message sent*/
@@ -104,18 +104,18 @@
 #define IS_SOF			0x08				/* Sync off flag	*/
 
 /* Transfer period step (write) */
-#define REG_STP(x)		((x)->scsi.io_port + (6 << (x)->scsi.io_shift))
+#define REG_STP			(6)
 
 /* Synchronous Offset (write) */
-#define REG_SOF(x)		((x)->scsi.io_port + (7 << (x)->scsi.io_shift))
+#define REG_SOF			(7)
 
 /* Fifo state register (read) */
-#define REG_CFIS(x)		((x)->scsi.io_port + (7 << (x)->scsi.io_shift))
+#define REG_CFIS		(7)
 #define CFIS_CF			0x1f				/* Num bytes in FIFO	*/
 #define CFIS_IS			0xe0				/* Step			*/
 
 /* config register 1 */
-#define REG_CNTL1(x)		((x)->scsi.io_port + (8 << (x)->scsi.io_shift))
+#define REG_CNTL1		(8)
 #define CNTL1_CID		(7 << 0)			/* Chip ID			*/
 #define CNTL1_STE		(1 << 3)			/* Self test enable		*/
 #define CNTL1_PERE		(1 << 4)			/* Parity enable reporting en.	*/
@@ -124,7 +124,7 @@
 #define CNTL1_ETM		(1 << 7)			/* Extended Timing Mode		*/
 
 /* Clock conversion factor (read) */
-#define REG_CLKF(x)		((x)->scsi.io_port + (9 << (x)->scsi.io_shift))
+#define REG_CLKF		(9)
 #define CLKF_F37MHZ		0x00				/* 35.01 - 40 MHz		*/
 #define CLKF_F10MHZ		0x02				/* 10 MHz			*/
 #define CLKF_F12MHZ		0x03				/* 10.01 - 15 MHz		*/
@@ -134,13 +134,13 @@
 #define CLKF_F32MHZ		0x07				/* 30.01 - 35 MHz		*/
 
 /* Chip test register (write) */
-#define REG0_FTM(x)		((x)->scsi.io_port + (10 << (x)->scsi.io_shift))
+#define REG_FTM			(10)
 #define TEST_FTM		0x01				/* Force target mode		*/
 #define TEST_FIM		0x02				/* Force initiator mode		*/
 #define TEST_FHI		0x04				/* Force high impedance mode	*/
 
 /* Configuration register 2 (read/write) */
-#define REG_CNTL2(x)		((x)->scsi.io_port + (11 << (x)->scsi.io_shift))
+#define REG_CNTL2		(11)
 #define CNTL2_PGDP		(1 << 0)			/* Pass Th/Generate Data Parity	*/
 #define CNTL2_PGRP		(1 << 1)			/* Pass Th/Generate Reg Parity	*/
 #define CNTL2_ACDPE		(1 << 2)			/* Abort on Cmd/Data Parity Err	*/
@@ -151,7 +151,7 @@
 #define CNTL2_DAE		(1 << 7)			/* Data Alignment Enable	*/
 
 /* Configuration register 3 (read/write) */
-#define REG_CNTL3(x)		((x)->scsi.io_port + (12 << (x)->scsi.io_shift))
+#define REG_CNTL3		(12)
 #define CNTL3_BS8		(1 << 0)			/* Burst size 8			*/
 #define CNTL3_MDM		(1 << 1)			/* Modify DMA mode		*/
 #define CNTL3_LBTM		(1 << 2)			/* Last Byte Transfer mode	*/
@@ -162,14 +162,14 @@
 #define CNTL3_ADIDCHK		(1 << 7)			/* Additional ID check		*/
 
 /* High transfer count (read/write) */
-#define REG_CTCH(x)		((x)->scsi.io_port + (14 << (x)->scsi.io_shift))
-#define REG_STCH(x)		((x)->scsi.io_port + (14 << (x)->scsi.io_shift))
+#define REG_CTCH		(14)
+#define REG_STCH		(14)
 
-/* ID reigster (read only) */
-#define REG1_ID(x)		((x)->scsi.io_port + (14 << (x)->scsi.io_shift))
+/* ID register (read only) */
+#define REG_ID			(14)
 
 /* Data alignment */
-#define REG0_DAL(x)		((x)->scsi.io_port + (15 << (x)->scsi.io_shift))
+#define REG_DAL			(15)
 
 typedef enum {
 	PHASE_IDLE,					/* we're not planning on doing anything	*/
@@ -212,6 +212,9 @@ typedef enum {
 #define MAGIC	0x441296bdUL
 #define NR_MSGS	8
 
+#define FASCAP_DMA		(1 << 0)
+#define FASCAP_PSEUDODMA	(1 << 1)
+
 typedef struct {
 	unsigned long		magic_start;
 	spinlock_t		host_lock;
@@ -233,12 +236,13 @@ typedef struct {
 
 	/* driver information */
 	struct {
+		phase_t		phase;			/* current phase			*/
+		void		*io_base;		/* iomem base of FAS216			*/
 		unsigned int	io_port;		/* base address of FAS216		*/
 		unsigned int	io_shift;		/* shift to adjust reg offsets by	*/
-		unsigned int	irq;			/* interrupt				*/
 		unsigned char	cfg[4];			/* configuration registers		*/
 		const char	*type;			/* chip type				*/
-		phase_t		phase;			/* current phase			*/
+		unsigned int	irq;			/* interrupt				*/
 
 		struct {
 			unsigned char	target;		/* reconnected target			*/
@@ -253,7 +257,6 @@ typedef struct {
 		unsigned int	async_stp;		/* Async transfer STP value		*/
 		unsigned char	msgin_fifo;		/* bytes in fifo at time of message in	*/
 		unsigned char	message[256];		/* last message received from device	*/
-		unsigned int	msglen;			/* length of last message received	*/
 
 		unsigned char	disconnectable:1;	/* this command can be disconnected	*/
 		unsigned char	aborting:1;		/* aborting command			*/
@@ -281,6 +284,7 @@ typedef struct {
 		unsigned char	wide_max_size;		/* Maximum wide transfer size		*/
 		unsigned char	cntl3;			/* Control Reg 3			*/
 		unsigned int	asyncperiod;		/* Async transfer period (ns)		*/
+		unsigned int	capabilities;		/* driver capabilities			*/
 		unsigned int	disconnect_ok:1;	/* Disconnects allowed?			*/
 	} ifcfg;
 
@@ -319,26 +323,18 @@ typedef struct {
 } FAS216_Info;
 
 /* Function: int fas216_init (struct Scsi_Host *instance)
- * Purpose : initialise FAS/NCR/AMD SCSI ic.
+ * Purpose : initialise FAS/NCR/AMD SCSI structures.
  * Params  : instance - a driver-specific filled-out structure
  * Returns : 0 on success
  */
 extern int fas216_init (struct Scsi_Host *instance);
 
-/* Function: int fas216_abort (Scsi_Cmnd *SCpnt)
- * Purpose : abort a command if something horrible happens.
- * Params  : SCpnt - Command that is believed to be causing a problem.
- * Returns : one of SCSI_ABORT_ macros.
- */
-extern int fas216_abort (Scsi_Cmnd *);
-
-/* Function: int fas216_reset (Scsi_Cmnd *SCpnt, unsigned int reset_flags)
- * Purpose : resets the adapter if something horrible happens.
- * Params  : SCpnt - Command that is believed to be causing a problem.
- *	     reset_flags - flags indicating reset type that is believed to be required.
- * Returns : one of SCSI_RESET_ macros, or'd with the SCSI_RESET_*_RESET macros.
+/* Function: int fas216_add (struct Scsi_Host *instance, struct device *dev)
+ * Purpose : initialise FAS/NCR/AMD SCSI ic.
+ * Params  : instance - a driver-specific filled-out structure
+ * Returns : 0 on success
  */
-extern int fas216_reset (Scsi_Cmnd *, unsigned int);
+extern int fas216_add (struct Scsi_Host *instance, struct device *dev);
 
 /* Function: int fas216_queue_command (Scsi_Cmnd *SCpnt, void (*done)(Scsi_Cmnd *))
  * Purpose : queue a command for adapter to process.
@@ -355,20 +351,21 @@ extern int fas216_queue_command (Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  */
 extern int fas216_command (Scsi_Cmnd *);
 
-/* Function: void fas216_intr (struct Scsi_Host *instance)
+/* Function: void fas216_intr (FAS216_Info *info)
  * Purpose : handle interrupts from the interface to progress a command
- * Params  : instance - interface to service
+ * Params  : info - interface to service
  */
-extern void fas216_intr (struct Scsi_Host *instance);
+extern void fas216_intr (FAS216_Info *info);
+
+extern void fas216_remove (struct Scsi_Host *instance);
 
-/* Function: int fas216_release (struct Scsi_Host *instance)
+/* Function: void fas216_release (struct Scsi_Host *instance)
  * Purpose : release all resources and put everything to bed for FAS/NCR/AMD SCSI ic.
  * Params  : instance - a driver-specific filled-out structure
  * Returns : 0 on success
  */
-extern int fas216_release (struct Scsi_Host *instance);
+extern void fas216_release (struct Scsi_Host *instance);
 
-extern int fas216_info(FAS216_Info *info, char *buffer);
 extern int fas216_print_host(FAS216_Info *info, char *buffer);
 extern int fas216_print_stats(FAS216_Info *info, char *buffer);
 extern int fas216_print_device(FAS216_Info *info, Scsi_Device *scd, char *buffer);

drivers/acorn/scsi/oak.c

@@ -192,7 +192,8 @@ static struct ecard_driver oakscsi_driver = {
 	.remove		= __devexit_p(oakscsi_remove),
 	.id_table	= oakscsi_cids,
 	.drv = {
-		.name	= "oakscsi",
+		.devclass	= &shost_devclass,
+		.name		= "oakscsi",
 	},
 };
 

drivers/acorn/scsi/scsi.h

@@ -55,8 +55,6 @@ static inline unsigned char get_next_SCp_byte(Scsi_Pointer *SCp)
 
 	SCp->ptr += 1;
 	SCp->this_residual -= 1;
-	if (SCp->this_residual == 0)
-		next_SCp(SCp);
 
 	return c;
 }
@@ -66,8 +64,6 @@ static inline void put_next_SCp_byte(Scsi_Pointer *SCp, unsigned char c)
 	*SCp->ptr = c;
 	SCp->ptr += 1;
 	SCp->this_residual -= 1;
-	if (SCp->this_residual == 0)
-		next_SCp(SCp);
 }
 
 static inline void init_SCp(Scsi_Cmnd *SCpnt)
@@ -112,7 +108,7 @@ static inline void init_SCp(Scsi_Cmnd *SCpnt)
 	 * we aren't interested in the buffer pointer.
 	 */
 	if (SCpnt->SCp.this_residual == 0 && SCpnt->SCp.ptr) {
-#ifdef BELT_AND_BRACES
+#if 0 //def BELT_AND_BRACES
 		printk(KERN_WARNING "scsi%d.%c: zero length buffer passed for "
 		       "command ", SCpnt->host->host_no, '0' + SCpnt->target);
 		print_command(SCpnt->cmnd);

drivers/input/mouse/rpcmouse.c

@@ -88,7 +88,7 @@ static int __init rpcmouse_init(void)
 
 	input_register_device(&rpcmouse_dev);
 
-	printk(KERN_INFO "input: Acorn RiscPC mouse irq %d", IRQ_VSYNCPULSE);
+	printk(KERN_INFO "input: Acorn RiscPC mouse\n");
 
 	return 0;
 }

drivers/mtd/maps/sa1100-flash.c

@@ -512,6 +512,37 @@ static void h3xxx_set_vpp(struct map_info *map, int vpp)
 #define h3xxx_set_vpp NULL
 #endif
 
+#ifdef CONFIG_SA1100_HACKKIT
+static struct mtd_partition hackkit_partitions[] = {
+	{
+		.name		= "BLOB",
+		.size		= 0x00040000,
+		.offset		= 0x00000000,
+		.mask_flags	= MTD_WRITEABLE,  /* force read-only */
+	}, {
+		.name		= "config",
+		.size		= 0x00040000,
+		.offset		= MTDPART_OFS_APPEND,
+	}, {
+		.name		= "kernel",
+		.size		= 0x00100000,
+		.offset		= MTDPART_OFS_APPEND,
+	}, {
+		.name		= "initrd",
+		.size		= 0x00180000,
+		.offset		= MTDPART_OFS_APPEND,
+	}, {
+		.name		= "rootfs",
+		.size		= 0x700000,
+		.offset		= MTDPART_OFS_APPEND,
+	}, {
+		.name		= "data",
+		.size		= MTDPART_SIZ_FULL,
+		.offset		= MTDPART_OFS_APPEND,
+	}
+};
+#endif
+
 #ifdef CONFIG_SA1100_HUW_WEBPANEL
 static struct mtd_partition huw_webpanel_partitions[] = {
 	{
@@ -849,6 +880,12 @@ static int __init sa1100_static_partitions(struct mtd_partition **parts)
 		nb_parts     = ARRAY_SIZE(h3xxx_partitions);
 	}
 #endif
+#ifdef CONFIG_SA1100_HACKKIT
+	if (machine_is_hackkit()) {
+		*parts = hackkit_partitions;
+		nb_parts = ARRAY_SIZE(hackkit_partitions);
+	}
+#endif
 #ifdef CONFIG_SA1100_HUW_WEBPANEL
 	if (machine_is_huw_webpanel()) {
 		*parts       = huw_webpanel_partitions;

drivers/pcmcia/sa1100_trizeps.c

@@ -13,7 +13,8 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 
-#include <asm/hardware.h>   // included trizeps.h
+#include <asm/hardware.h>
+#include <asm/arch/trizeps.h>
 #include <asm/mach-types.h>
 #include <asm/system.h>
 #include <asm/irq.h>
@@ -54,7 +55,7 @@ static int trizeps_pcmcia_init(struct pcmcia_init *init)
 	return NUMBER_OF_TRIZEPS_PCMCIA_SLOTS;
 
  irq_err:
-	printk( KERN_ERR __FUNCTION__ ": PCMCIA Request for IRQ %u failed\n", TRIZEPS_IRQ_PCMCIA_CD0 );
+	printk( KERN_ERR "%s(): PCMCIA Request for IRQ %u failed\n", __FUNCTION__, TRIZEPS_IRQ_PCMCIA_CD0 );
 	return -1;
 }
 

drivers/serial/uart00.c

 /*
- *  linux/drivers/char/uart00.c
+ *  linux/drivers/serial/uart00.c
  *
  *  Driver for UART00 serial ports
  *
@@ -149,7 +149,7 @@ uart00_rx_chars(struct uart_port *port, struct pt_regs *regs)
 			goto ignore_char;
 	} else if (rds & UART_RDS_PE_MSK)
 		port->icount.parity++;
-	else if (rds & UART_RDS_PE_MSK)
+	else if (rds & UART_RDS_FE_MSK)
 		port->icount.frame++;
 	if (rds & UART_RDS_OE_MSK)
 		port->icount.overrun++;
@@ -168,7 +168,7 @@ uart00_rx_chars(struct uart_port *port, struct pt_regs *regs)
 	else if (rds & UART_RDS_FE_MSK)
 		flg = TTY_FRAME;
 
-	if (status & UART_RDS_OE_MSK) {
+	if (rds & UART_RDS_OE_MSK) {
 		/*
 		 * CHECK: does overrun affect the current character?
 		 * ASSUMPTION: it does not.

drivers/video/acornfb.c

@@ -896,6 +896,7 @@ static struct fb_ops acornfb_ops = {
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
 	.fb_mmap	= acornfb_mmap,
+	.fb_cursor	= soft_cursor,
 };
 
 /*

drivers/video/sa1100fb.c

@@ -1122,6 +1122,7 @@ static struct fb_ops sa1100fb_ops = {
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
 	.fb_blank	= sa1100fb_blank,
+	.fb_cursor	= soft_cursor,
 };
 
 /*

include/asm-arm/arch-ebsa110/param.h

 /*
  *  linux/include/asm-arm/arch-ebsa110/param.h
  */
+#define __KERNEL_HZ	200

include/asm-arm/arch-ebsa110/time.h

@@ -17,17 +17,80 @@
  */
 
 #include <asm/leds.h>
+#include <asm/io.h>
 
-extern int  ebsa110_reset_timer(void);
-extern void ebsa110_setup_timer(void);
+extern unsigned long (*gettimeoffset)(void);
+
+#define PIT_CTRL		(PIT_BASE + 0x0d)
+#define PIT_T2			(PIT_BASE + 0x09)
+#define PIT_T1			(PIT_BASE + 0x05)
+#define PIT_T0			(PIT_BASE + 0x01)
+
+/*
+ * This is the rate at which your MCLK signal toggles (in Hz)
+ * This was measured on a 10 digit frequency counter sampling
+ * over 1 second.
+ */
+#define MCLK	47894000
+
+/*
+ * This is the rate at which the PIT timers get clocked
+ */
+#define CLKBY7	(MCLK / 7)
+
+/*
+ * This is the counter value.  We tick at 200Hz on this platform.
+ */
+#define COUNT	((CLKBY7 + (HZ / 2)) / HZ)
+
+/*
+ * Get the time offset from the system PIT.  Note that if we have missed an
+ * interrupt, then the PIT counter will roll over (ie, be negative).
+ * This actually works out to be convenient.
+ */
+static unsigned long ebsa110_gettimeoffset(void)
+{
+	unsigned long offset, count;
+
+	__raw_writeb(0x40, PIT_CTRL);
+	count = __raw_readb(PIT_T1);
+	count |= __raw_readb(PIT_T1) << 8;
+
+	/*
+	 * If count > COUNT, make the number negative.
+	 */
+	if (count > COUNT)
+		count |= 0xffff0000;
+
+	offset = COUNT;
+	offset -= count;
+
+	/*
+	 * `offset' is in units of timer counts.  Convert
+	 * offset to units of microseconds.
+	 */
+	offset = offset * (1000000 / HZ) / COUNT;
+
+	return offset;
+}
 
 static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
-	if (ebsa110_reset_timer()) {
-		do_leds();
-		do_timer(regs);
-		do_profile(regs);
-	}
+	u32 count;
+
+	/* latch and read timer 1 */
+	__raw_writeb(0x40, PIT_CTRL);
+	count = __raw_readb(PIT_T1);
+	count |= __raw_readb(PIT_T1) << 8;
+
+	count += COUNT;
+
+	__raw_writeb(count & 0xff, PIT_T1);
+	__raw_writeb(count >> 8, PIT_T1);
+
+	do_leds();
+	do_timer(regs);
+	do_profile(regs);
 }
 
 /*
@@ -35,7 +98,14 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  */
 void __init time_init(void)
 {
-	ebsa110_setup_timer();
+	/*
+	 * Timer 1, mode 2, LSB/MSB
+	 */
+	__raw_writeb(0x70, PIT_CTRL);
+	__raw_writeb(COUNT & 0xff, PIT_T1);
+	__raw_writeb(COUNT >> 8, PIT_T1);
+
+	gettimeoffset = ebsa110_gettimeoffset;
 
 	timer_irq.handler = timer_interrupt;
 

include/asm-arm/arch-rpc/hardware.h

@@ -63,6 +63,17 @@
 #define IO_EC_MEMC8_BASE	0x8000ac00
 #define IO_EC_MEMC_BASE		0x80000000
 
+#define NETSLOT_BASE		0x0302b000
+#define NETSLOT_SIZE		0x00001000
+
+#define PODSLOT_IOC0_BASE	0x03240000
+#define PODSLOT_IOC4_BASE	0x03270000
+#define PODSLOT_IOC_SIZE	(1 << 14)
+#define PODSLOT_MEMC_BASE	0x03000000
+#define PODSLOT_MEMC_SIZE	(1 << 14)
+#define PODSLOT_EASI_BASE	0x08000000
+#define PODSLOT_EASI_SIZE	(1 << 24)
+
 #define	EXPMASK_STATUS		(EXPMASK_BASE + 0x00)
 #define EXPMASK_ENABLE		(EXPMASK_BASE + 0x04)
 

include/asm-arm/arch-rpc/io.h

@@ -247,4 +247,9 @@ DECLARE_IO(int,l,"")
 #define outsb(p,d,l)	__raw_writesb(__ioaddr(p),d,l)
 #define outsw(p,d,l)	__raw_writesw(__ioaddr(p),d,l)
 
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)	(x)
+
 #endif

include/asm-arm/arch-sa1100/ide.h

@@ -49,8 +49,9 @@ ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
 		*irq = 0;
 }
 
-
-
+#ifdef CONFIG_SA1100_TRIZEPS
+#include <asm/arch/trizeps.h>
+#endif
 
 /*
  * This registers the standard ports for this architecture with the IDE
@@ -124,6 +125,23 @@ ide_init_default_hwifs(void)
         ide_register_hw(&hw);
 #endif
     }
-}
+    else if( machine_is_trizeps() ){
+#ifdef CONFIG_SA1100_TRIZEPS
+	hw_regs_t hw;
 
+	/* Enable appropriate GPIOs as interrupt lines */
+	GPDR &= ~GPIO_GPIO(TRIZEPS_IRQ_IDE);
+	set_irq_type( TRIZEPS_IRQ_IDE, IRQT_RISING );
 
+	/* set the pcmcia interface timing */
+	//MECR = 0x00060006; // Done on trizeps init
+
+	/* Take hard drives out of reset */
+	GPSR = GPIO_GPIO(TRIZEPS_IRQ_IDE);
+
+	ide_init_hwif_ports(&hw, TRIZEPS_IDE_CS0 + 0, TRIZEPS_IDE_CS1 + 6, NULL);
+	hw.irq = TRIZEPS_IRQ_IDE;
+	ide_register_hw(&hw, NULL);
+#endif
+    }
+}

include/asm-arm/arch-sa1100/mftb2.h

+#ifndef _ARCH_ARM_MFTB2_h_
+#define _ARCH_ARM_MFTB2_h_
+
+// Defines for arch/arm/mm/mm-sa1100.h
+#define TRIZEPS_PHYS_VIRT_MAP_SIZE   0x00800000l
+
+// physical address (only for mm-sa1100.h)
+#define TRIZEPS_PHYS_IO_BASE         0x30000000l
+#define TRIZEPS_PHYS_MEM_BASE        0x38000000l
+
+// virtual
+#define TRIZEPS_IO_BASE		     0xF0000000l
+#define TRIZEPS_MEM_BASE             0xF2000000l
+
+// Offsets for phys and virtual
+#define TRIZEPS_OFFSET_REG0          0x00300000l
+#define TRIZEPS_OFFSET_REG1          0x00380000l
+#define TRIZEPS_OFFSET_IDE_CS0       0x00000000l
+#define TRIZEPS_OFFSET_IDE_CS1       0x00080000l
+#define TRIZEPS_OFFSET_UART5         0x00100000l
+#define TRIZEPS_OFFSET_UART6         0x00180000l
+#define TRIZEPS_PHYS_REG0            (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_REG0)
+#define TRIZEPS_PHYS_REG1            (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_REG1)
+#define TRIZEPS_PHYS_IDE_CS0         (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_IDE_CS0)
+#define TRIZEPS_PHYS_IDE_CS1         (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_IDE_CS1)
+#define TRIZEPS_PHYS_UART5           (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_UART5)
+#define TRIZEPS_PHYS_UART6           (TRIZEPS_PHYS_IO_BASE + TRIZEPS_OFFSET_UART6)
+
+// Use follow defines in devices
+// virtual address
+#define TRIZEPS_REG0    (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_REG0)
+#define TRIZEPS_REG1    (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_REG1)
+#define TRIZEPS_IDE_CS0 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_IDE_CS0)
+#define TRIZEPS_IDE_CS1 (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_IDE_CS1)
+#define TRIZEPS_UART5   (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_UART5)
+#define TRIZEPS_UART6   (TRIZEPS_IO_BASE + TRIZEPS_OFFSET_UART6)
+
+#define TRIZEPS_BAUD_BASE 1500000
+
+//#if 0 //temporarily disabled
+#ifndef __ASSEMBLY__
+struct tri_uart_cts_data_t {
+    int cts_gpio;
+    int cts_prev_state;
+    struct uart_info *info;
+    struct uart_port *port;
+    const char *name;
+};
+#endif /* __ASSEMBLY__ */
+
+/* Defines for MFTB2 serial_sa1100.c hardware handshaking lines */
+#define SERIAL_FULL
+#define NOT_CONNECTED	0
+#ifdef SERIAL_FULL
+#define TRIZEPS_GPIO_UART1_RTS	GPIO_GPIO14
+#define TRIZEPS_GPIO_UART1_DTR	NOT_CONNECTED //GPIO_GPIO9
+#define TRIZEPS_GPIO_UART1_CTS	GPIO_GPIO15
+#define TRIZEPS_GPIO_UART1_DCD	NOT_CONNECTED //GPIO_GPIO2
+#define TRIZEPS_GPIO_UART1_DSR	NOT_CONNECTED //GPIO_GPIO3
+#define TRIZEPS_GPIO_UART3_RTS	NOT_CONNECTED //GPIO_GPIO7
+#define TRIZEPS_GPIO_UART3_DTR	NOT_CONNECTED //GPIO_GPIO8
+#define TRIZEPS_GPIO_UART3_CTS	NOT_CONNECTED //GPIO_GPIO4
+#define TRIZEPS_GPIO_UART3_DCD	NOT_CONNECTED //GPIO_GPIO5
+#define TRIZEPS_GPIO_UART3_DSR	NOT_CONNECTED //GPIO_GPIO6
+
+#define TRIZEPS_GPIO_UART2_RTS	NOT_CONNECTED //GPIO_GPIO7
+#define TRIZEPS_GPIO_UART2_DTR	NOT_CONNECTED //GPIO_GPIO8
+#define TRIZEPS_GPIO_UART2_CTS	NOT_CONNECTED //GPIO_GPIO4
+#define TRIZEPS_GPIO_UART2_DCD	NOT_CONNECTED //GPIO_GPIO5
+#define TRIZEPS_GPIO_UART2_DSR	NOT_CONNECTED //GPIO_GPIO6
+
+#define TRIZEPS_IRQ_UART1_CTS	IRQ_GPIO15
+#define TRIZEPS_IRQ_UART1_DCD	NO_IRQ //IRQ_GPIO2
+#define TRIZEPS_IRQ_UART1_DSR	NO_IRQ //IRQ_GPIO3
+#define TRIZEPS_IRQ_UART3_CTS	NO_IRQ //IRQ_GPIO4
+#define TRIZEPS_IRQ_UART3_DCD	NO_IRQ //IRQ_GPIO5
+#define TRIZEPS_IRQ_UART3_DSR	NO_IRQ //IRQ_GPIO6
+
+#define TRIZEPS_IRQ_UART2_CTS	NO_IRQ //IRQ_GPIO4
+#define TRIZEPS_IRQ_UART2_DCD	NO_IRQ //IRQ_GPIO5
+#define TRIZEPS_IRQ_UART2_DSR	NO_IRQ //IRQ_GPIO6
+
+#endif /* SERIAL_FULL */
+//#endif //0
+
+/*
+ * This section contains the defines for the MFTB2 implementation
+ * of drivers/ide/hd.c. HD_IOBASE_0 and HD_IOBASE_1 have to be
+ * adjusted if hardware changes.
+ */
+#define TRIZEPS_IRQ_IDE 10		/* MFTB2 specific */
+
+/*---   ROOT   ---*/
+#define TRIZEPS_GPIO_ROOT_NFS       0
+#define TRIZEPS_GPIO_ROOT_HD        21
+/*---  PCMCIA  ---*/
+#define TRIZEPS_GPIO_PCMCIA_IRQ0 1
+#define TRIZEPS_GPIO_PCMCIA_CD0  24
+#define TRIZEPS_IRQ_PCMCIA_IRQ0  TRIZEPS_GPIO_PCMCIA_IRQ0
+#define TRIZEPS_IRQ_PCMCIA_CD0   TRIZEPS_GPIO_PCMCIA_CD0 + 32 - 11
+
+// REGISTER 0 -> 0x0XXXX (16bit access)
+// read only
+#define TRIZEPS_A_STAT             0x8000l
+#define TRIZEPS_F_STAT             0x4000l
+#define TRIZEPS_BATT_FAULT_EN      0x2000l
+#define TRIZEPS_nDQ                0x1000l
+#define TRIZEPS_MFT_OFF            0x0800l
+#define TRIZEPS_D_APWOFF           0x0400l
+#define TRIZEPS_F_CTRL             0x0200l
+#define TRIZEPS_F_STOP             0x0100l
+
+// read / write
+#define TRIZEPS_KP_IR_EN           0x0080l
+#define TRIZEPS_FIR                0x0040l
+#define TRIZEPS_BAR_ON             0x0020l
+#define TRIZEPS_VCI_ON             0x0010l
+#define TRIZEPS_LED4               0x0008l
+#define TRIZEPS_LED3               0x0004l
+#define TRIZEPS_LED2               0x0002l
+#define TRIZEPS_LED1               0x0001l
+
+// REGISTER 1 -> 0x1XXXX (16bit access)
+// read only
+#define TRIZEPS_nVCI2              0x8000l
+#define TRIZEPS_nAB_LOW            0x4000l
+#define TRIZEPS_nMB_DEAD           0x2000l
+#define TRIZEPS_nMB_LOW            0x1000l
+#define TRIZEPS_nPCM_VS2           0x0800l
+#define TRIZEPS_nPCM_VS1           0x0400l
+#define TRIZEPS_PCM_BVD2           0x0200l
+#define TRIZEPS_PCM_BVD1           0x0100l
+
+// read / write
+#define TRIZEPS_nROOT_NFS          0x0080l
+#define TRIZEPS_nROOT_HD           0x0040l
+#define TRIZEPS_nPCM_ENA_REG       0x0020l
+#define TRIZEPS_nPCM_RESET_DISABLE 0x0010l
+#define TRIZEPS_PCM_EN0_REG        0x0008l
+#define TRIZEPS_PCM_EN1_REG        0x0004l
+#define TRIZEPS_PCM_V3_EN_REG      0x0002l
+#define TRIZEPS_PCM_V5_EN_REG      0x0001l
+
+/* Access to Board Control Register */
+#define TRIZEPS_BCR0 (*(volatile unsigned short *)(TRIZEPS_REG0))
+#define TRIZEPS_BCR1 (*(volatile unsigned short *)(TRIZEPS_REG1))
+
+#define TRIZEPS_BCR_set( reg, x ) do { \
+	unsigned long flags; \
+	local_irq_save(flags); \
+	(reg) |= (x); \
+	local_irq_restore(flags); \
+} while (0)
+
+#define TRIZEPS_BCR_clear( reg, x ) do { \
+	unsigned long flags; \
+	local_irq_save(flags); \
+	(reg) &= ~(x); \
+	local_irq_restore(flags); \
+} while (0)
+
+#define TRIZEPS_OFFSET_KP_REG      0x00200000l
+#define TRIZEPS_OFFSET_VCI2        0x00280000l
+#define TRIZEPS_OFFSET_VCI4        0x00400000l
+
+#define TRIZEPS_OFFSET_VCI2_1_DPR  (TRIZEPS_OFFSET_VCI2 + 0x00010000l)
+#define TRIZEPS_OFFSET_VCI2_2_DPR  (TRIZEPS_OFFSET_VCI2 + 0x00018000l)
+#define TRIZEPS_OFFSET_VCI2_1_SEMA (TRIZEPS_OFFSET_VCI2 + 0x00020000l)
+#define TRIZEPS_OFFSET_VCI2_2_SEMA (TRIZEPS_OFFSET_VCI2 + 0x00028000l)
+
+#define TRIZEPS_OFFSET_VCI4_1_DPR  (TRIZEPS_OFFSET_VCI4 + 0x00000000l)
+#define TRIZEPS_OFFSET_VCI4_2_DPR  (TRIZEPS_OFFSET_VCI4 + 0x00008000l)
+#define TRIZEPS_OFFSET_VCI4_1_SEMA (TRIZEPS_OFFSET_VCI4 + 0x00000380l)
+#define TRIZEPS_OFFSET_VCI4_2_SEMA (TRIZEPS_OFFSET_VCI4 + 0x00000388l)
+#define TRIZEPS_OFFSET_VCI4_1_CNTR (TRIZEPS_OFFSET_VCI4 + 0x00000390l)
+#define TRIZEPS_OFFSET_VCI4_2_CNTR (TRIZEPS_OFFSET_VCI4 + 0x00000392l)
+
+#define TRIZEPS_PHYS_KP_REG        (PHYS_TRIZEPS_IO_BASE + TRIZEPS_OFFSET_KP_REG)
+
+// VCI address
+#define TRIZEPS_PHYS_VCI2_1_DPR    (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_DPR)
+#define TRIZEPS_PHYS_VCI2_2_DPR    (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_DPR)
+#define TRIZEPS_PHYS_VCI2_1_SEMA   (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_SEMA)
+#define TRIZEPS_PHYS_VCI2_2_SEMA   (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_SEMA)
+
+// VCI4 address
+#define TRIZEPS_PHYS_VCI4_1_DPR    (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI4_1_DPR)
+#define TRIZEPS_PHYS_VCI4_2_DPR    (TRIZEPS_PHYS_MEM_BASE + TRIZEPS_OFFSET_VCI4_2_DPR)
+#define TRIZEPS_PHYS_VCI4_1_SEMA   (TRIZEPS_PHYS_IO_BASE  + TRIZEPS_OFFSET_VCI4_1_SEMA)
+#define TRIZEPS_PHYS_VCI4_2_SEMA   (TRIZEPS_PHYS_IO_BASE  + TRIZEPS_OFFSET_VCI4_2_SEMA)
+#define TRIZEPS_PHYS_VCI4_1_CNTR   (TRIZEPS_PHYS_IO_BASE  + TRIZEPS_OFFSET_VCI4_1_CNTR)
+#define TRIZEPS_PHYS_VCI4_2_CNTR   (TRIZEPS_PHYS_IO_BASE  + TRIZEPS_OFFSET_VCI4_2_CNTR)
+
+#define TRIZEPS_KP_REG               (TRIZEPS_IO_BASE  + TRIZEPS_OFFSET_KP_REG)
+
+// VCI address
+#define TRIZEPS_VCI2_1_DPR           (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_DPR)
+#define TRIZEPS_VCI2_2_DPR           (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_DPR)
+#define TRIZEPS_VCI2_1_SEMA          (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_1_SEMA)
+#define TRIZEPS_VCI2_2_SEMA          (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI2_2_SEMA)
+
+// VCI4 address
+#define TRIZEPS_VCI4_1_DPR           (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI4_1_DPR)
+#define TRIZEPS_VCI4_2_DPR           (TRIZEPS_MEM_BASE + TRIZEPS_OFFSET_VCI4_2_DPR)
+#define TRIZEPS_VCI4_1_SEMA          (TRIZEPS_IO_BASE  + TRIZEPS_OFFSET_VCI4_1_SEMA)
+#define TRIZEPS_VCI4_2_SEMA          (TRIZEPS_IO_BASE  + TRIZEPS_OFFSET_VCI4_2_SEMA)
+#define TRIZEPS_VCI4_1_CNTR          (TRIZEPS_IO_BASE  + TRIZEPS_OFFSET_VCI4_1_CNTR)
+#define TRIZEPS_VCI4_2_CNTR          (TRIZEPS_IO_BASE  + TRIZEPS_OFFSET_VCI4_2_CNTR)
+
+#endif