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Commit 4a15cdff authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'drm-nouveau-next' of... 

Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

- Ilia's PMPEG improvements
- MSI fixes, and another attempt at enabling by default
- Initial GK208 support, just modesetting
- "Old" PM code gone, new infrastructure and various different stages of support (depending which chipset / ram type etc) is in its place.  This includes support that goes beyond what the previous code was capable of.  User control has been deliberately sabotaged, it's not safe to use still.
- Thermal management / fan control that's been present for a while is turned ON by default now.
- Misc other fixes that have accumulated

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (74 commits)
  drm/nouveau/fb: implement various bits of work towards memory reclocking
  drm/nouveau: implement a simple sysfs interface to new pm code
  drm/nouveau/device: initial control object class, with pstate control methods
  drm/nouveau/clk: implement power state and engine clock control in core
  drm/nouveau/volt: implement voltage control in core
  drm/nouveau/bios: parsing for various tables required for power management
  drm/nouveau/perfmon: initial infrastructure to expose performance counters
  drm/nouveau/bus: add interfaces/helpers for sequencer
  drm/nouveau/bus: make external class definitions pointers
  drm/nouveau/pwr: initial implementation
  drm/nouveau/therm: update target fanspeed outside of therm lock
  drm/nouveau/therm: automatic mode by default
  drm/nouveau/therm: no toggle fan control either if we can't guarantee no pwm connected
  drm/nvc0/therm: allow fan control if we've killed the vbios ppwr ucode
  drm/nouveau/therm: if no bios trip/linear info, default to perf-suggested speed
  drm/nouveau/therm: add hook for clk to suggest fanspeed to therm
  drm/nouveau/pwr: assign a subdev id for upcoming implementation
  drm/nouveau/gpio: return different error code for not found vs invalid
  drm/nouveau/drm/pm: remove everything except the hwmon interfaces to THERM
  drm/nouveau/core: make all info-level messages silent for runtime pm
  ...
parents ec61f5eb aae95ca7
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drivers/gpu/drm/nouveau/Makefile
View file @ 4a15cdff
......@@ -28,7 +28,9 @@ nouveau-y += core/subdev/bar/nv50.o
nouveau-y += core/subdev/bar/nvc0.o
nouveau-y += core/subdev/bios/base.o
nouveau-y += core/subdev/bios/bit.o
nouveau-y += core/subdev/bios/boost.o
nouveau-y += core/subdev/bios/conn.o
nouveau-y += core/subdev/bios/cstep.o
nouveau-y += core/subdev/bios/dcb.o
nouveau-y += core/subdev/bios/disp.o
nouveau-y += core/subdev/bios/dp.o
......@@ -39,17 +41,26 @@ nouveau-y += core/subdev/bios/init.o
nouveau-y += core/subdev/bios/mxm.o
nouveau-y += core/subdev/bios/perf.o
nouveau-y += core/subdev/bios/pll.o
nouveau-y += core/subdev/bios/rammap.o
nouveau-y += core/subdev/bios/timing.o
nouveau-y += core/subdev/bios/therm.o
nouveau-y += core/subdev/bios/vmap.o
nouveau-y += core/subdev/bios/volt.o
nouveau-y += core/subdev/bios/xpio.o
nouveau-y += core/subdev/bus/hwsq.o
nouveau-y += core/subdev/bus/nv04.o
nouveau-y += core/subdev/bus/nv31.o
nouveau-y += core/subdev/bus/nv50.o
nouveau-y += core/subdev/bus/nv94.o
nouveau-y += core/subdev/bus/nvc0.o
nouveau-y += core/subdev/clock/base.o
nouveau-y += core/subdev/clock/nv04.o
nouveau-y += core/subdev/clock/nv40.o
nouveau-y += core/subdev/clock/nv50.o
nouveau-y += core/subdev/clock/nv84.o
nouveau-y += core/subdev/clock/nva3.o
nouveau-y += core/subdev/clock/nvc0.o
nouveau-y += core/subdev/clock/nve0.o
nouveau-y += core/subdev/clock/pllnv04.o
nouveau-y += core/subdev/clock/pllnva3.o
nouveau-y += core/subdev/devinit/base.o
......@@ -78,7 +89,12 @@ nouveau-y += core/subdev/fb/nv47.o
nouveau-y += core/subdev/fb/nv49.o
nouveau-y += core/subdev/fb/nv4e.o
nouveau-y += core/subdev/fb/nv50.o
nouveau-y += core/subdev/fb/nv84.o
nouveau-y += core/subdev/fb/nva3.o
nouveau-y += core/subdev/fb/nvaa.o
nouveau-y += core/subdev/fb/nvaf.o
nouveau-y += core/subdev/fb/nvc0.o
nouveau-y += core/subdev/fb/nve0.o
nouveau-y += core/subdev/fb/ramnv04.o
nouveau-y += core/subdev/fb/ramnv10.o
nouveau-y += core/subdev/fb/ramnv1a.o
......@@ -89,7 +105,12 @@ nouveau-y += core/subdev/fb/ramnv44.o
nouveau-y += core/subdev/fb/ramnv49.o
nouveau-y += core/subdev/fb/ramnv4e.o
nouveau-y += core/subdev/fb/ramnv50.o
nouveau-y += core/subdev/fb/ramnva3.o
nouveau-y += core/subdev/fb/ramnvaa.o
nouveau-y += core/subdev/fb/ramnvc0.o
nouveau-y += core/subdev/fb/ramnve0.o
nouveau-y += core/subdev/fb/sddr3.o
nouveau-y += core/subdev/fb/gddr5.o
nouveau-y += core/subdev/gpio/base.o
nouveau-y += core/subdev/gpio/nv10.o
nouveau-y += core/subdev/gpio/nv50.o
......@@ -113,13 +134,22 @@ nouveau-y += core/subdev/instmem/nv50.o
nouveau-y += core/subdev/ltcg/nvc0.o
nouveau-y += core/subdev/mc/base.o
nouveau-y += core/subdev/mc/nv04.o
nouveau-y += core/subdev/mc/nv40.o
nouveau-y += core/subdev/mc/nv44.o
nouveau-y += core/subdev/mc/nv50.o
nouveau-y += core/subdev/mc/nv94.o
nouveau-y += core/subdev/mc/nv98.o
nouveau-y += core/subdev/mc/nvc0.o
nouveau-y += core/subdev/mc/nvc3.o
nouveau-y += core/subdev/mxm/base.o
nouveau-y += core/subdev/mxm/mxms.o
nouveau-y += core/subdev/mxm/nv50.o
nouveau-y += core/subdev/pwr/base.o
nouveau-y += core/subdev/pwr/memx.o
nouveau-y += core/subdev/pwr/nva3.o
nouveau-y += core/subdev/pwr/nvc0.o
nouveau-y += core/subdev/pwr/nvd0.o
nouveau-y += core/subdev/pwr/nv108.o
nouveau-y += core/subdev/therm/base.o
nouveau-y += core/subdev/therm/fan.o
nouveau-y += core/subdev/therm/fannil.o
......@@ -140,6 +170,9 @@ nouveau-y += core/subdev/vm/nv41.o
nouveau-y += core/subdev/vm/nv44.o
nouveau-y += core/subdev/vm/nv50.o
nouveau-y += core/subdev/vm/nvc0.o
nouveau-y += core/subdev/volt/base.o
nouveau-y += core/subdev/volt/gpio.o
nouveau-y += core/subdev/volt/nv40.o
nouveau-y += core/engine/falcon.o
nouveau-y += core/engine/xtensa.o
......@@ -158,6 +191,7 @@ nouveau-y += core/engine/copy/nve0.o
nouveau-y += core/engine/crypt/nv84.o
nouveau-y += core/engine/crypt/nv98.o
nouveau-y += core/engine/device/base.o
nouveau-y += core/engine/device/ctrl.o
nouveau-y += core/engine/device/nv04.o
nouveau-y += core/engine/device/nv10.o
nouveau-y += core/engine/device/nv20.o
......@@ -227,8 +261,18 @@ nouveau-y += core/engine/graph/nve4.o
nouveau-y += core/engine/graph/nvf0.o
nouveau-y += core/engine/mpeg/nv31.o
nouveau-y += core/engine/mpeg/nv40.o
nouveau-y += core/engine/mpeg/nv44.o
nouveau-y += core/engine/mpeg/nv50.o
nouveau-y += core/engine/mpeg/nv84.o
nouveau-y += core/engine/perfmon/base.o
nouveau-y += core/engine/perfmon/daemon.o
nouveau-y += core/engine/perfmon/nv40.o
nouveau-y += core/engine/perfmon/nv50.o
nouveau-y += core/engine/perfmon/nv84.o
nouveau-y += core/engine/perfmon/nva3.o
nouveau-y += core/engine/perfmon/nvc0.o
nouveau-y += core/engine/perfmon/nve0.o
nouveau-y += core/engine/perfmon/nvf0.o
nouveau-y += core/engine/ppp/nv98.o
nouveau-y += core/engine/ppp/nvc0.o
nouveau-y += core/engine/software/nv04.o
......@@ -260,9 +304,7 @@ include $(src)/dispnv04/Makefile
nouveau-y += nv50_display.o
# drm/pm
nouveau-y += nouveau_pm.o nouveau_volt.o nouveau_perf.o
nouveau-y += nv04_pm.o nv40_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o
nouveau-y += nouveau_mem.o
nouveau-y += nouveau_hwmon.o nouveau_sysfs.o
# other random bits
nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
......
drivers/gpu/drm/nouveau/core/core/event.c
View file @ 4a15cdff
......@@ -23,62 +23,114 @@
#include <core/os.h>
#include <core/event.h>
static void
nouveau_event_put_locked(struct nouveau_event *event, int index,
struct nouveau_eventh *handler)
void
nouveau_event_put(struct nouveau_eventh *handler)
{
if (!--event->index[index].refs) {
if (event->disable)
event->disable(event, index);
struct nouveau_event *event = handler->event;
unsigned long flags;
if (__test_and_clear_bit(NVKM_EVENT_ENABLE, &handler->flags)) {
spin_lock_irqsave(&event->refs_lock, flags);
if (!--event->index[handler->index].refs) {
if (event->disable)
event->disable(event, handler->index);
}
spin_unlock_irqrestore(&event->refs_lock, flags);
}
list_del(&handler->head);
}
void
nouveau_event_put(struct nouveau_event *event, int index,
struct nouveau_eventh *handler)
nouveau_event_get(struct nouveau_eventh *handler)
{
struct nouveau_event *event = handler->event;
unsigned long flags;
if (!__test_and_set_bit(NVKM_EVENT_ENABLE, &handler->flags)) {
spin_lock_irqsave(&event->refs_lock, flags);
if (!event->index[handler->index].refs++) {
if (event->enable)
event->enable(event, handler->index);
}
spin_unlock_irqrestore(&event->refs_lock, flags);
}
}
spin_lock_irqsave(&event->lock, flags);
if (index < event->index_nr)
nouveau_event_put_locked(event, index, handler);
spin_unlock_irqrestore(&event->lock, flags);
static void
nouveau_event_fini(struct nouveau_eventh *handler)
{
struct nouveau_event *event = handler->event;
unsigned long flags;
nouveau_event_put(handler);
spin_lock_irqsave(&event->list_lock, flags);
list_del(&handler->head);
spin_unlock_irqrestore(&event->list_lock, flags);
}
void
nouveau_event_get(struct nouveau_event *event, int index,
struct nouveau_eventh *handler)
static int
nouveau_event_init(struct nouveau_event *event, int index,
int (*func)(void *, int), void *priv,
struct nouveau_eventh *handler)
{
unsigned long flags;
spin_lock_irqsave(&event->lock, flags);
if (index < event->index_nr) {
list_add(&handler->head, &event->index[index].list);
if (!event->index[index].refs++) {
if (event->enable)
event->enable(event, index);
}
if (index >= event->index_nr)
return -EINVAL;
handler->event = event;
handler->flags = 0;
handler->index = index;
handler->func = func;
handler->priv = priv;
spin_lock_irqsave(&event->list_lock, flags);
list_add_tail(&handler->head, &event->index[index].list);
spin_unlock_irqrestore(&event->list_lock, flags);
return 0;
}
int
nouveau_event_new(struct nouveau_event *event, int index,
int (*func)(void *, int), void *priv,
struct nouveau_eventh **phandler)
{
struct nouveau_eventh *handler;
int ret = -ENOMEM;
handler = *phandler = kmalloc(sizeof(*handler), GFP_KERNEL);
if (handler) {
ret = nouveau_event_init(event, index, func, priv, handler);
if (ret)
kfree(handler);
}
spin_unlock_irqrestore(&event->lock, flags);
return ret;
}
void
nouveau_event_ref(struct nouveau_eventh *handler, struct nouveau_eventh **ref)
{
BUG_ON(handler != NULL);
if (*ref) {
nouveau_event_fini(*ref);
kfree(*ref);
}
*ref = handler;
}
void
nouveau_event_trigger(struct nouveau_event *event, int index)
{
struct nouveau_eventh *handler, *temp;
struct nouveau_eventh *handler;
unsigned long flags;
if (index >= event->index_nr)
if (WARN_ON(index >= event->index_nr))
return;
spin_lock_irqsave(&event->lock, flags);
list_for_each_entry_safe(handler, temp, &event->index[index].list, head) {
if (handler->func(handler, index) == NVKM_EVENT_DROP) {
nouveau_event_put_locked(event, index, handler);
}
spin_lock_irqsave(&event->list_lock, flags);
list_for_each_entry(handler, &event->index[index].list, head) {
if (test_bit(NVKM_EVENT_ENABLE, &handler->flags) &&
handler->func(handler->priv, index) == NVKM_EVENT_DROP)
nouveau_event_put(handler);
}
spin_unlock_irqrestore(&event->lock, flags);
spin_unlock_irqrestore(&event->list_lock, flags);
}
void
......@@ -102,7 +154,8 @@ nouveau_event_create(int index_nr, struct nouveau_event **pevent)
if (!event)
return -ENOMEM;
spin_lock_init(&event->lock);
spin_lock_init(&event->list_lock);
spin_lock_init(&event->refs_lock);
for (i = 0; i < index_nr; i++)
INIT_LIST_HEAD(&event->index[i].list);
event->index_nr = index_nr;
......
drivers/gpu/drm/nouveau/core/core/option.c
View file @ 4a15cdff
......@@ -25,15 +25,6 @@
#include <core/option.h>
#include <core/debug.h>
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
static inline int
strncasecmpz(const char *str, const char *cmp, size_t len)
{
if (strlen(cmp) != len)
return len;
return strncasecmp(str, cmp, len);
}
const char *
nouveau_stropt(const char *optstr, const char *opt, int *arglen)
{
......@@ -105,7 +96,7 @@ nouveau_dbgopt(const char *optstr, const char *sub)
else if (!strncasecmpz(optstr, "warn", len))
level = NV_DBG_WARN;
else if (!strncasecmpz(optstr, "info", len))
level = NV_DBG_INFO;
level = NV_DBG_INFO_NORMAL;
else if (!strncasecmpz(optstr, "debug", len))
level = NV_DBG_DEBUG;
else if (!strncasecmpz(optstr, "trace", len))
......
drivers/gpu/drm/nouveau/core/core/printk.c
View file @ 4a15cdff
......@@ -27,16 +27,38 @@
#include <core/subdev.h>
#include <core/printk.h>
int nv_printk_suspend_level = NV_DBG_DEBUG;
int nv_info_debug_level = NV_DBG_INFO_NORMAL;
void
nv_printk_(struct nouveau_object *object, const char *pfx, int level,
const char *fmt, ...)
nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
{
static const char name[] = { '!', 'E', 'W', ' ', 'D', 'T', 'P', 'S' };
const char *pfx;
char mfmt[256];
va_list args;
switch (level) {
case NV_DBG_FATAL:
pfx = KERN_CRIT;
break;
case NV_DBG_ERROR:
pfx = KERN_ERR;
break;
case NV_DBG_WARN:
pfx = KERN_WARNING;
break;
case NV_DBG_INFO_NORMAL:
pfx = KERN_INFO;
break;
case NV_DBG_DEBUG:
case NV_DBG_PARANOIA:
case NV_DBG_TRACE:
case NV_DBG_SPAM:
default:
pfx = KERN_DEBUG;
break;
}
if (object && !nv_iclass(object, NV_CLIENT_CLASS)) {
struct nouveau_object *device = object;
struct nouveau_object *subdev = object;
......@@ -74,20 +96,3 @@ nv_printk_(struct nouveau_object *object, const char *pfx, int level,
vprintk(mfmt, args);
va_end(args);
}
#define CONV_LEVEL(x) case NV_DBG_##x: return NV_PRINTK_##x
const char *nv_printk_level_to_pfx(int level)
{
switch (level) {
CONV_LEVEL(FATAL);
CONV_LEVEL(ERROR);
CONV_LEVEL(WARN);
CONV_LEVEL(INFO);
CONV_LEVEL(DEBUG);
CONV_LEVEL(PARANOIA);
CONV_LEVEL(TRACE);
CONV_LEVEL(SPAM);
}
return NV_PRINTK_DEBUG;
}
drivers/gpu/drm/nouveau/core/engine/device/base.c
View file @ 4a15cdff
......@@ -29,7 +29,7 @@
#include <core/class.h>
#include <engine/device.h>
#include "priv.h"
static DEFINE_MUTEX(nv_devices_mutex);
static LIST_HEAD(nv_devices);
......@@ -75,7 +75,9 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE,
[NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE,
[NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE,
[NVDEV_SUBDEV_PWR] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_PERFMON] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO,
[NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO,
[NVDEV_ENGINE_GR] = NV_DEVICE_DISABLE_GRAPH,
......@@ -87,7 +89,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_PPP] = NV_DEVICE_DISABLE_PPP,
[NVDEV_ENGINE_COPY0] = NV_DEVICE_DISABLE_COPY0,
[NVDEV_ENGINE_COPY1] = NV_DEVICE_DISABLE_COPY1,
[NVDEV_ENGINE_UNK1C1] = NV_DEVICE_DISABLE_UNK1C1,
[NVDEV_ENGINE_VIC] = NV_DEVICE_DISABLE_VIC,
[NVDEV_ENGINE_VENC] = NV_DEVICE_DISABLE_VENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_DISABLE_DISP,
[NVDEV_SUBDEV_NR] = 0,
......@@ -119,10 +121,12 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
return -ENODEV;
}
ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL,
ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
nouveau_control_oclass,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_FIFO) |
(1ULL << NVDEV_ENGINE_DISP), &devobj);
(1ULL << NVDEV_ENGINE_DISP) |
(1ULL << NVDEV_ENGINE_PERFMON), &devobj);
*pobject = nv_object(devobj);
if (ret)
return ret;
......@@ -158,22 +162,29 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
iounmap(map);
/* determine chipset and derive architecture from it */
if ((boot0 & 0x0f000000) > 0) {
device->chipset = (boot0 & 0xff00000) >> 20;
switch (device->chipset & 0xf0) {
case 0x10: device->card_type = NV_10; break;
case 0x20: device->card_type = NV_20; break;
case 0x30: device->card_type = NV_30; break;
case 0x40:
case 0x60: device->card_type = NV_40; break;
case 0x50:
case 0x80:
case 0x90:
case 0xa0: device->card_type = NV_50; break;
case 0xc0: device->card_type = NV_C0; break;
case 0xd0: device->card_type = NV_D0; break;
case 0xe0:
case 0xf0: device->card_type = NV_E0; break;
if ((boot0 & 0x1f000000) > 0) {
device->chipset = (boot0 & 0x1ff00000) >> 20;
switch (device->chipset & 0x1f0) {
case 0x010: {
if (0x461 & (1 << (device->chipset & 0xf)))
device->card_type = NV_10;
else
device->card_type = NV_11;
break;
}
case 0x020: device->card_type = NV_20; break;
case 0x030: device->card_type = NV_30; break;
case 0x040:
case 0x060: device->card_type = NV_40; break;
case 0x050:
case 0x080:
case 0x090:
case 0x0a0: device->card_type = NV_50; break;
case 0x0c0: device->card_type = NV_C0; break;
case 0x0d0: device->card_type = NV_D0; break;
case 0x0e0:
case 0x0f0:
case 0x100: device->card_type = NV_E0; break;
default:
break;
}
......@@ -188,7 +199,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
switch (device->card_type) {
case NV_04: ret = nv04_identify(device); break;
case NV_10: ret = nv10_identify(device); break;
case NV_10:
case NV_11: ret = nv10_identify(device); break;
case NV_20: ret = nv20_identify(device); break;
case NV_30: ret = nv30_identify(device); break;
case NV_40: ret = nv40_identify(device); break;
......@@ -212,7 +224,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
nv_info(device, "Family : NV%02X\n", device->card_type);
/* determine frequency of timing crystal */
if ( device->chipset < 0x17 ||
if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
(device->chipset >= 0x20 && device->chipset < 0x25))
strap &= 0x00000040;
else
......
drivers/gpu/drm/nouveau/core/engine/device/ctrl.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include <core/object.h>
#include <core/class.h>
#include <subdev/clock.h>
#include "priv.h"
static int
nouveau_control_mthd_pstate_info(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_clock *clk = nouveau_clock(object);
struct nv_control_pstate_info *args = data;
if (size < sizeof(*args))
return -EINVAL;
if (clk) {
args->count = clk->state_nr;
args->ustate = clk->ustate;
args->pstate = clk->pstate;
} else {
args->count = 0;
args->ustate = NV_CONTROL_PSTATE_INFO_USTATE_DISABLE;
args->pstate = NV_CONTROL_PSTATE_INFO_PSTATE_UNKNOWN;
}
return 0;
}
static int
nouveau_control_mthd_pstate_attr(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_clock *clk = nouveau_clock(object);
struct nv_control_pstate_attr *args = data;
struct nouveau_clocks *domain;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
int i = 0, j = -1;
u32 lo, hi;
if ((size < sizeof(*args)) || !clk ||
(args->state >= 0 && args->state >= clk->state_nr))
return -EINVAL;
domain = clk->domains;
while (domain->name != nv_clk_src_max) {
if (domain->mname && ++j == args->index)
break;
domain++;
}
if (domain->name == nv_clk_src_max)
return -EINVAL;
if (args->state != NV_CONTROL_PSTATE_ATTR_STATE_CURRENT) {
list_for_each_entry(pstate, &clk->states, head) {
if (i++ == args->state)
break;
}
lo = pstate->base.domain[domain->name];
hi = lo;
list_for_each_entry(cstate, &pstate->list, head) {
lo = min(lo, cstate->domain[domain->name]);
hi = max(hi, cstate->domain[domain->name]);
}
args->state = pstate->pstate;
} else {
lo = max(clk->read(clk, domain->name), 0);
hi = lo;
}
snprintf(args->name, sizeof(args->name), "%s", domain->mname);
snprintf(args->unit, sizeof(args->unit), "MHz");
args->min = lo / domain->mdiv;
args->max = hi / domain->mdiv;
args->index = 0;
while ((++domain)->name != nv_clk_src_max) {
if (domain->mname) {
args->index = ++j;
break;
}
}
return 0;
}
static int
nouveau_control_mthd_pstate_user(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_clock *clk = nouveau_clock(object);
struct nv_control_pstate_user *args = data;
if (size < sizeof(*args) || !clk)
return -EINVAL;
return nouveau_clock_ustate(clk, args->state);
}
struct nouveau_oclass
nouveau_control_oclass[] = {
{ .handle = NV_CONTROL_CLASS,
.ofuncs = &nouveau_object_ofuncs,
.omthds = (struct nouveau_omthds[]) {
{ NV_CONTROL_PSTATE_INFO,
NV_CONTROL_PSTATE_INFO, nouveau_control_mthd_pstate_info },
{ NV_CONTROL_PSTATE_ATTR,
NV_CONTROL_PSTATE_ATTR, nouveau_control_mthd_pstate_attr },
{ NV_CONTROL_PSTATE_USER,
NV_CONTROL_PSTATE_USER, nouveau_control_mthd_pstate_user },
{},
},
},
{}
};
drivers/gpu/drm/nouveau/core/engine/device/nv04.c
View file @ 4a15cdff
......@@ -50,15 +50,15 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv04_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -68,15 +68,15 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv04_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......
drivers/gpu/drm/nouveau/core/engine/device/nv10.c
View file @ 4a15cdff
......@@ -52,10 +52,10 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
......@@ -69,15 +69,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -88,15 +88,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -107,15 +107,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -126,15 +126,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -145,15 +145,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -164,15 +164,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -183,15 +183,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......
drivers/gpu/drm/nouveau/core/engine/device/nv20.c
View file @ 4a15cdff
......@@ -53,15 +53,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -72,15 +72,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -91,15 +91,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -110,15 +110,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......
drivers/gpu/drm/nouveau/core/engine/device/nv30.c
View file @ 4a15cdff
......@@ -53,15 +53,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -72,15 +72,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
......@@ -91,15 +91,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
......@@ -111,15 +111,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
......@@ -131,15 +131,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
......
drivers/gpu/drm/nouveau/core/engine/device/priv.h 0 → 100644
View file @ 4a15cdff
#ifndef __NVKM_DEVICE_PRIV_H__
#define __NVKM_DEVICE_PRIV_H__
#include <engine/device.h>
extern struct nouveau_oclass nouveau_control_oclass[];
#endif
drivers/gpu/drm/nouveau/core/engine/disp/dport.c
View file @ 4a15cdff
......@@ -70,17 +70,10 @@ dp_set_link_config(struct dp_state *dp)
};
u32 lnkcmp;
u8 sink[2];
int ret;
DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
/* set desired link configuration on the sink */
sink[0] = dp->link_bw / 27000;
sink[1] = dp->link_nr;
if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
nv_wraux(dp->aux, DPCD_LC00, sink, 2);
/* set desired link configuration on the source */
if ((lnkcmp = dp->info.lnkcmp)) {
if (dp->version < 0x30) {
......@@ -96,10 +89,22 @@ dp_set_link_config(struct dp_state *dp)
nvbios_exec(&init);
}
return dp->func->lnk_ctl(dp->disp, dp->outp, dp->head,
dp->link_nr, dp->link_bw / 27000,
dp->dpcd[DPCD_RC02] &
DPCD_RC02_ENHANCED_FRAME_CAP);
ret = dp->func->lnk_ctl(dp->disp, dp->outp, dp->head,
dp->link_nr, dp->link_bw / 27000,
dp->dpcd[DPCD_RC02] &
DPCD_RC02_ENHANCED_FRAME_CAP);
if (ret) {
ERR("lnk_ctl failed with %d\n", ret);
return ret;
}
/* set desired link configuration on the sink */
sink[0] = dp->link_bw / 27000;
sink[1] = dp->link_nr;
if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
return nv_wraux(dp->aux, DPCD_LC00, sink, 2);
}
static void
......@@ -294,8 +299,17 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
ret = nv_rdaux(dp->aux, 0x00000, dp->dpcd, sizeof(dp->dpcd));
if (ret) {
/* it's possible the display has been unplugged before we
* get here. we still need to execute the full set of
* vbios scripts, and program the OR at a high enough
* frequency to satisfy the target mode. failure to do
* so results at best in an UPDATE hanging, and at worst
* with PDISP running away to join the circus.
*/
dp->dpcd[1] = link_bw[0] / 27000;
dp->dpcd[2] = 4;
dp->dpcd[3] = 0x00;
ERR("failed to read DPCD\n");
return ret;
}
/* adjust required bandwidth for 8B/10B coding overhead */
......@@ -308,7 +322,7 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
while (*link_bw > (dp->dpcd[1] * 27000))
link_bw++;
while (link_bw[0]) {
while ((ret = -EIO) && link_bw[0]) {
/* find minimum required lane count at this link rate */
dp->link_nr = dp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT;
while ((dp->link_nr >> 1) * link_bw[0] > datarate)
......@@ -328,8 +342,10 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
!dp_link_train_eq(dp))
break;
} else
if (ret >= 1) {
/* dp_set_link_config() handled training */
if (ret) {
/* dp_set_link_config() handled training, or
* we failed to communicate with the sink.
*/
break;
}
......@@ -339,8 +355,10 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
/* finish link training */
dp_set_training_pattern(dp, 0);
if (ret < 0)
ERR("link training failed\n");
/* execute post-train script from vbios */
dp_link_train_fini(dp);
return true;
return (ret < 0) ? false : true;
}
drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
View file @ 4a15cdff
......@@ -59,6 +59,7 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
struct nv04_disp_priv *priv = (void *)subdev;
u32 crtc0 = nv_rd32(priv, 0x600100);
u32 crtc1 = nv_rd32(priv, 0x602100);
u32 pvideo;
if (crtc0 & 0x00000001) {
nouveau_event_trigger(priv->base.vblank, 0);
......@@ -69,6 +70,14 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
nouveau_event_trigger(priv->base.vblank, 1);
nv_wr32(priv, 0x602100, 0x00000001);
}
if (nv_device(priv)->chipset >= 0x10 &&
nv_device(priv)->chipset <= 0x40) {
pvideo = nv_rd32(priv, 0x8100);
if (pvideo & ~0x11)
nv_info(priv, "PVIDEO intr: %08x\n", pvideo);
nv_wr32(priv, 0x8100, pvideo);
}
}
static int
......
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
View file @ 4a15cdff
......@@ -541,6 +541,15 @@ nvd0_disp_base_init(struct nouveau_object *object)
nv_wr32(priv, 0x6100a0, 0x00000000);
nv_wr32(priv, 0x6100b0, 0x00000307);
/* disable underflow reporting, preventing an intermittent issue
* on some nve4 boards where the production vbios left this
* setting enabled by default.
*
* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
*/
for (i = 0; i < priv->head.nr; i++)
nv_mask(priv, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
return 0;
}
......
drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
View file @ 4a15cdff
......@@ -97,8 +97,9 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
{
struct nouveau_bios *bios = nouveau_bios(disp);
struct nv50_disp_priv *priv = (void *)disp;
const u32 shift = nv94_sor_dp_lane_map(priv, lane);
const u32 loff = nv94_sor_loff(outp);
u32 addr, shift = nv94_sor_dp_lane_map(priv, lane);
u32 addr, data[3];
u8 ver, hdr, cnt, len;
struct nvbios_dpout info;
struct nvbios_dpcfg ocfg;
......@@ -113,9 +114,12 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
if (!addr)
return -EINVAL;
nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift);
nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift);
nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8);
data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(priv, 0x61c130 + loff) & ~(0x0000ff00);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.drv << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pre << shift));
nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.unk << 8));
return 0;
}
......
drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
View file @ 4a15cdff
......@@ -93,8 +93,9 @@ nvd0_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
{
struct nouveau_bios *bios = nouveau_bios(disp);
struct nv50_disp_priv *priv = (void *)disp;
const u32 shift = nvd0_sor_dp_lane_map(priv, lane);
const u32 loff = nvd0_sor_loff(outp);
u32 addr, shift = nvd0_sor_dp_lane_map(priv, lane);
u32 addr, data[3];
u8 ver, hdr, cnt, len;
struct nvbios_dpout info;
struct nvbios_dpcfg ocfg;
......@@ -109,9 +110,12 @@ nvd0_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
if (!addr)
return -EINVAL;
nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift);
nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift);
nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8);
data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(priv, 0x61c130 + loff) & ~(0x0000ff00);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.drv << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pre << shift));
nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.unk << 8));
nv_mask(priv, 0x61c13c + loff, 0x00000000, 0x00000000);
return 0;
}
......
drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
View file @ 4a15cdff
......@@ -632,8 +632,8 @@ nv04_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv04_fifo_oclass = {
struct nouveau_oclass *
nv04_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
View file @ 4a15cdff
......@@ -159,8 +159,8 @@ nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv10_fifo_oclass = {
struct nouveau_oclass *
nv10_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv10_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
View file @ 4a15cdff
......@@ -196,8 +196,8 @@ nv17_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv17_fifo_oclass = {
struct nouveau_oclass *
nv17_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x17),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv17_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
View file @ 4a15cdff
......@@ -337,8 +337,8 @@ nv40_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv40_fifo_oclass = {
struct nouveau_oclass *
nv40_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
View file @ 4a15cdff
......@@ -502,8 +502,8 @@ nv50_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv50_fifo_oclass = {
struct nouveau_oclass *
nv50_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
View file @ 4a15cdff
......@@ -144,7 +144,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
case NVDEV_ENGINE_CRYPT :
case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
default:
return -EINVAL;
......@@ -180,7 +180,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_UNK1C1), &chan);
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
......@@ -243,7 +243,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_UNK1C1), &chan);
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
......@@ -435,8 +435,8 @@ nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv84_fifo_oclass = {
struct nouveau_oclass *
nv84_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x84),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv84_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
View file @ 4a15cdff
......@@ -720,8 +720,8 @@ nvc0_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nvc0_fifo_oclass = {
struct nouveau_oclass *
nvc0_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
View file @ 4a15cdff
......@@ -675,8 +675,8 @@ nve0_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nve0_fifo_oclass = {
struct nouveau_oclass *
nve0_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_fifo_ctor,
......
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
View file @ 4a15cdff
......@@ -587,6 +587,7 @@ nvc1_grctx_init_unk58xx[] = {
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
......@@ -598,6 +599,7 @@ nvc1_grctx_init_rop[] = {
{ 0x408904, 1, 0x04, 0x62000001 },
{ 0x408908, 1, 0x04, 0x00c80929 },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
static struct nvc0_graph_init
......@@ -671,6 +673,7 @@ nvc1_grctx_init_gpc_0[] = {
{ 0x419000, 1, 0x04, 0x00000780 },
{ 0x419004, 2, 0x04, 0x00000000 },
{ 0x419014, 1, 0x04, 0x00000004 },
{}
};
static struct nvc0_graph_init
......@@ -717,6 +720,7 @@ nvc1_grctx_init_tpc[] = {
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00011110 },
{ 0x419f30, 11, 0x04, 0x00000000 },
{}
};
void
......
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
View file @ 4a15cdff
......@@ -258,6 +258,7 @@ nvd7_grctx_init_hub[] = {
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvd9_grctx_init_rop,
NULL
};
struct nvc0_graph_init *
......
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
View file @ 4a15cdff
......@@ -466,6 +466,7 @@ nvd9_grctx_init_hub[] = {
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvd9_grctx_init_rop,
NULL
};
struct nvc0_graph_init *
......
drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
View file @ 4a15cdff
......@@ -945,7 +945,8 @@ nv10_graph_load_context(struct nv10_graph_chan *chan, int chid)
for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]);
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]);
}
......@@ -970,7 +971,8 @@ nv10_graph_unload_context(struct nv10_graph_chan *chan)
for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]);
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]);
}
......@@ -1052,7 +1054,8 @@ nv10_graph_context_ctor(struct nouveau_object *parent,
NV_WRITE_CTX(0x00400e14, 0x00001000);
NV_WRITE_CTX(0x00400e30, 0x00080008);
NV_WRITE_CTX(0x00400e34, 0x00080008);
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
/* is it really needed ??? */
NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
nv_rd32(priv, NV10_PGRAPH_DEBUG_4));
......@@ -1231,7 +1234,7 @@ nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_engine(priv)->sclass = nv10_graph_sclass;
else
if (nv_device(priv)->chipset < 0x17 ||
nv_device(priv)->chipset == 0x1a)
nv_device(priv)->card_type < NV_11)
nv_engine(priv)->sclass = nv15_graph_sclass;
else
nv_engine(priv)->sclass = nv17_graph_sclass;
......@@ -1270,7 +1273,8 @@ nv10_graph_init(struct nouveau_object *object)
nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000);
nv_wr32(priv, 0x400a10, 0x03ff3fb6);
nv_wr32(priv, 0x400838, 0x002f8684);
......
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file @ 4a15cdff
......@@ -1138,7 +1138,7 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
nv_subdev(priv)->unit = 0x18001000;
nv_subdev(priv)->unit = 0x08001000;
nv_subdev(priv)->intr = nvc0_graph_intr;
priv->base.units = nvc0_graph_units;
......
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
View file @ 4a15cdff
......@@ -34,16 +34,7 @@
#include <engine/fifo.h>
#include <engine/mpeg.h>
#include <engine/graph/nv40.h>
struct nv31_mpeg_priv {
struct nouveau_mpeg base;
atomic_t refcount;
};
struct nv31_mpeg_chan {
struct nouveau_object base;
};
#include <engine/mpeg/nv31.h>
/*******************************************************************************
* MPEG object classes
......@@ -89,18 +80,18 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
if (mthd == 0x0190) {
/* DMA_CMD */
nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0);
nv_wr32(priv, 0x00b334, base);
nv_wr32(priv, 0x00b324, size);
} else
if (mthd == 0x01a0) {
/* DMA_DATA */
nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0);
nv_wr32(priv, 0x00b360, base);
nv_wr32(priv, 0x00b364, size);
} else {
/* DMA_IMAGE, VRAM only */
if (dma0 & 0x000c0000)
if (dma0 & 0x00030000)
return -EINVAL;
nv_wr32(priv, 0x00b370, base);
......@@ -110,7 +101,7 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
return 0;
}
static struct nouveau_ofuncs
struct nouveau_ofuncs
nv31_mpeg_ofuncs = {
.ctor = nv31_mpeg_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
......@@ -146,16 +137,23 @@ nv31_mpeg_context_ctor(struct nouveau_object *parent,
{
struct nv31_mpeg_priv *priv = (void *)engine;
struct nv31_mpeg_chan *chan;
unsigned long flags;
int ret;
if (!atomic_add_unless(&priv->refcount, 1, 1))
return -EBUSY;
ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
if (priv->chan) {
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
nouveau_object_destroy(&chan->base);
*pobject = NULL;
return -EBUSY;
}
priv->chan = chan;
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
return 0;
}
......@@ -164,11 +162,15 @@ nv31_mpeg_context_dtor(struct nouveau_object *object)
{
struct nv31_mpeg_priv *priv = (void *)object->engine;
struct nv31_mpeg_chan *chan = (void *)object;
atomic_dec(&priv->refcount);
unsigned long flags;
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
priv->chan = NULL;
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
nouveau_object_destroy(&chan->base);
}
static struct nouveau_oclass
struct nouveau_oclass
nv31_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x31),
.ofuncs = &(struct nouveau_ofuncs) {
......@@ -197,21 +199,19 @@ nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i)
void
nv31_mpeg_intr(struct nouveau_subdev *subdev)
{
struct nv31_mpeg_priv *priv = (void *)subdev;
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle;
struct nv31_mpeg_priv *priv = (void *)subdev;
u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
struct nouveau_object *engctx;
u32 stat = nv_rd32(priv, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234);
u32 data = nv_rd32(priv, 0x00b238);
u32 show = stat;
int chid;
unsigned long flags;
engctx = nouveau_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
engctx = nv_object(priv->chan);
if (stat & 0x01000000) {
/* happens on initial binding of the object */
......@@ -220,7 +220,7 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
show &= ~0x01000000;
}
if (type == 0x00000010) {
if (type == 0x00000010 && engctx) {
handle = nouveau_handle_get_class(engctx, 0x3174);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x01000000;
......@@ -232,13 +232,12 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
nv_wr32(priv, 0x00b230, 0x00000001);
if (show) {
nv_error(priv,
"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
chid, inst << 4, nouveau_client_name(engctx), stat,
type, mthd, data);
nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
pfifo->chid(pfifo, engctx),
nouveau_client_name(engctx), stat, type, mthd, data);
}
nouveau_engctx_put(engctx);
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
}
static int
......@@ -284,10 +283,7 @@ nv31_mpeg_init(struct nouveau_object *object)
/* PMPEG init */
nv_wr32(priv, 0x00b32c, 0x00000000);
nv_wr32(priv, 0x00b314, 0x00000100);
if (nv_device(priv)->chipset >= 0x40 && nv44_graph_class(priv))
nv_wr32(priv, 0x00b220, 0x00000044);
else
nv_wr32(priv, 0x00b220, 0x00000031);
nv_wr32(priv, 0x00b220, 0x00000031);
nv_wr32(priv, 0x00b300, 0x02001ec1);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
......
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h 0 → 100644
View file @ 4a15cdff
#ifndef __NV31_MPEG_H__
#define __NV31_MPEG_H__
#include <engine/mpeg.h>
struct nv31_mpeg_chan {
struct nouveau_object base;
};
struct nv31_mpeg_priv {
struct nouveau_mpeg base;
struct nv31_mpeg_chan *chan;
};
#endif
drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
View file @ 4a15cdff
......@@ -31,66 +31,63 @@
#include <subdev/instmem.h>
#include <engine/mpeg.h>
#include <engine/graph/nv40.h>
struct nv40_mpeg_priv {
struct nouveau_mpeg base;
};
struct nv40_mpeg_chan {
struct nouveau_mpeg_chan base;
};
#include <engine/mpeg/nv31.h>
/*******************************************************************************
* PMPEG context
* MPEG object classes
******************************************************************************/
static int
nv40_mpeg_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
{
struct nv40_mpeg_chan *chan;
int ret;
ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL,
264 * 4, 16,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
struct nouveau_instmem *imem = nouveau_instmem(object);
struct nv31_mpeg_priv *priv = (void *)object->engine;
u32 inst = *(u32 *)arg << 4;
u32 dma0 = nv_ro32(imem, inst + 0);
u32 dma1 = nv_ro32(imem, inst + 4);
u32 dma2 = nv_ro32(imem, inst + 8);
u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
u32 size = dma1 + 1;
/* only allow linear DMA objects */
if (!(dma0 & 0x00002000))
return -EINVAL;
if (mthd == 0x0190) {
/* DMA_CMD */
nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
nv_wr32(priv, 0x00b334, base);
nv_wr32(priv, 0x00b324, size);
} else
if (mthd == 0x01a0) {
/* DMA_DATA */
nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
nv_wr32(priv, 0x00b360, base);
nv_wr32(priv, 0x00b364, size);
} else {
/* DMA_IMAGE, VRAM only */
if (dma0 & 0x00030000)
return -EINVAL;
nv_wr32(priv, 0x00b370, base);
nv_wr32(priv, 0x00b374, size);
}
nv_wo32(&chan->base.base, 0x78, 0x02001ec1);
return 0;
}
static int
nv40_mpeg_context_fini(struct nouveau_object *object, bool suspend)
{
struct nv40_mpeg_priv *priv = (void *)object->engine;
struct nv40_mpeg_chan *chan = (void *)object;
u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000);
if (nv_rd32(priv, 0x00b318) == inst)
nv_mask(priv, 0x00b318, 0x80000000, 0x00000000);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
return 0;
}
static struct nouveau_omthds
nv40_mpeg_omthds[] = {
{ 0x0190, 0x0190, nv40_mpeg_mthd_dma },
{ 0x01a0, 0x01a0, nv40_mpeg_mthd_dma },
{ 0x01b0, 0x01b0, nv40_mpeg_mthd_dma },
{}
};
static struct nouveau_oclass
nv40_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_mpeg_context_ctor,
.dtor = _nouveau_mpeg_context_dtor,
.init = _nouveau_mpeg_context_init,
.fini = nv40_mpeg_context_fini,
.rd32 = _nouveau_mpeg_context_rd32,
.wr32 = _nouveau_mpeg_context_wr32,
},
struct nouveau_oclass
nv40_mpeg_sclass[] = {
{ 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds },
{}
};
/*******************************************************************************
......@@ -100,7 +97,7 @@ nv40_mpeg_cclass = {
static void
nv40_mpeg_intr(struct nouveau_subdev *subdev)
{
struct nv40_mpeg_priv *priv = (void *)subdev;
struct nv31_mpeg_priv *priv = (void *)subdev;
u32 stat;
if ((stat = nv_rd32(priv, 0x00b100)))
......@@ -117,7 +114,7 @@ nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv40_mpeg_priv *priv;
struct nv31_mpeg_priv *priv;
int ret;
ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
......@@ -127,8 +124,8 @@ nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nv40_mpeg_intr;
nv_engine(priv)->cclass = &nv40_mpeg_cclass;
nv_engine(priv)->sclass = nv31_mpeg_sclass;
nv_engine(priv)->cclass = &nv31_mpeg_cclass;
nv_engine(priv)->sclass = nv40_mpeg_sclass;
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
return 0;
}
......
drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/os.h>
#include <core/class.h>
#include <core/client.h>
#include <core/engctx.h>
#include <core/handle.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <subdev/instmem.h>
#include <engine/fifo.h>
#include <engine/mpeg.h>
struct nv44_mpeg_priv {
struct nouveau_mpeg base;
};
struct nv44_mpeg_chan {
struct nouveau_mpeg_chan base;
};
/*******************************************************************************
* PMPEG context
******************************************************************************/
static int
nv44_mpeg_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv44_mpeg_chan *chan;
int ret;
ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL,
264 * 4, 16,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
nv_wo32(&chan->base.base, 0x78, 0x02001ec1);
return 0;
}
static int
nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend)
{
struct nv44_mpeg_priv *priv = (void *)object->engine;
struct nv44_mpeg_chan *chan = (void *)object;
u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000);
if (nv_rd32(priv, 0x00b318) == inst)
nv_mask(priv, 0x00b318, 0x80000000, 0x00000000);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
return 0;
}
static struct nouveau_oclass
nv44_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x44),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv44_mpeg_context_ctor,
.dtor = _nouveau_mpeg_context_dtor,
.init = _nouveau_mpeg_context_init,
.fini = nv44_mpeg_context_fini,
.rd32 = _nouveau_mpeg_context_rd32,
.wr32 = _nouveau_mpeg_context_wr32,
},
};
/*******************************************************************************
* PMPEG engine/subdev functions
******************************************************************************/
static void
nv44_mpeg_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle;
struct nv44_mpeg_priv *priv = (void *)subdev;
u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
u32 stat = nv_rd32(priv, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234);
u32 data = nv_rd32(priv, 0x00b238);
u32 show = stat;
int chid;
engctx = nouveau_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x01000000) {
/* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) {
nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
show &= ~0x01000000;
}
if (type == 0x00000010) {
handle = nouveau_handle_get_class(engctx, 0x3174);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x01000000;
nouveau_handle_put(handle);
}
}
nv_wr32(priv, 0x00b100, stat);
nv_wr32(priv, 0x00b230, 0x00000001);
if (show) {
nv_error(priv,
"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
chid, inst << 4, nouveau_client_name(engctx), stat,
type, mthd, data);
}
nouveau_engctx_put(engctx);
}
static void
nv44_mpeg_me_intr(struct nouveau_subdev *subdev)
{
struct nv44_mpeg_priv *priv = (void *)subdev;
u32 stat;
if ((stat = nv_rd32(priv, 0x00b100)))
nv44_mpeg_intr(subdev);
if ((stat = nv_rd32(priv, 0x00b800))) {
nv_error(priv, "PMSRCH 0x%08x\n", stat);
nv_wr32(priv, 0x00b800, stat);
}
}
static int
nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv44_mpeg_priv *priv;
int ret;
ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nv44_mpeg_me_intr;
nv_engine(priv)->cclass = &nv44_mpeg_cclass;
nv_engine(priv)->sclass = nv40_mpeg_sclass;
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
return 0;
}
struct nouveau_oclass
nv44_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x44),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv44_mpeg_ctor,
.dtor = _nouveau_mpeg_dtor,
.init = nv31_mpeg_init,
.fini = _nouveau_mpeg_fini,
},
};
drivers/gpu/drm/nouveau/core/engine/perfmon/base.c 0 → 100644
View file @ 4a15cdff
This diff is collapsed.
drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static void
pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
u32 mask = 0x00000000;
u32 ctrl = 0x00000001;
int i;
for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
mask |= 1 << (ctr->signal[i] - dom->signal);
nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
}
static void
pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
ctr->ctr = ppm->pwr[ctr->slot];
ctr->clk = ppm->pwr[ppm->last];
}
static void
pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
int i;
for (i = 0; i <= ppm->last; i++) {
ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
}
}
static const struct nouveau_funcdom
pwr_perfctr_func = {
.init = pwr_perfctr_init,
.read = pwr_perfctr_read,
.next = pwr_perfctr_next,
};
const struct nouveau_specdom
nva3_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nouveau_specdom
nvc0_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nouveau_specdom
nve0_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{ 0x15, "pwr_ce2_idle" },
{}
}, &pwr_perfctr_func },
{}
};
drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static void
nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
struct nv40_perfmon_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
for (i = 0; i < 4 && ctr->signal[i]; i++)
src |= (ctr->signal[i] - dom->signal) << (i * 8);
nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001);
nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src);
nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log);
}
static void
nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
struct nv40_perfmon_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break;
case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break;
case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break;
case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break;
}
cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr);
}
static void
nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
if (priv->sequence != ppm->sequence) {
nv_wr32(priv, 0x400084, 0x00000020);
priv->sequence = ppm->sequence;
}
}
const struct nouveau_funcdom
nv40_perfctr_func = {
.init = nv40_perfctr_init,
.read = nv40_perfctr_read,
.next = nv40_perfctr_next,
};
static const struct nouveau_specdom
nv40_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
int
nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv40_perfmon_oclass *mclass = (void *)oclass;
struct nv40_perfmon_priv *priv;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
return 0;
}
struct nouveau_oclass *
nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x40),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv40_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h 0 → 100644
View file @ 4a15cdff
#ifndef __NVKM_PM_NV40_H__
#define __NVKM_PM_NV40_H__
#include "priv.h"
struct nv40_perfmon_oclass {
struct nouveau_oclass base;
const struct nouveau_specdom *doms;
};
struct nv40_perfmon_priv {
struct nouveau_perfmon base;
u32 sequence;
};
int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *data, u32 size,
struct nouveau_object **pobject);
struct nv40_perfmon_cntr {
struct nouveau_perfctr base;
};
extern const struct nouveau_funcdom nv40_perfctr_func;
#endif
drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nv50_perfmon[] = {
{ 0x040, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{ 0xc8, "gr_idle" },
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x020, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x040, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv50_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nv84_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv84_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nva3_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
static int
nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **object)
{
int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object);
if (ret == 0) {
struct nv40_perfmon_priv *priv = (void *)*object;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nva3_perfmon_pwr);
if (ret)
return ret;
priv->base.last = 3;
}
return ret;
}
struct nouveau_oclass *
nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva3_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nva3_perfmon,
}.base;
drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nvc0_perfmon_hub[] = {
{}
};
static const struct nouveau_specdom
nvc0_perfmon_gpc[] = {
{}
};
static const struct nouveau_specdom
nvc0_perfmon_part[] = {
{}
};
static void
nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
struct nvc0_perfmon_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
for (i = 0; i < 4 && ctr->signal[i]; i++)
src |= (ctr->signal[i] - dom->signal) << (i * 8);
nv_wr32(priv, dom->addr + 0x09c, 0x00040002);
nv_wr32(priv, dom->addr + 0x100, 0x00000000);
nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src);
nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log);
}
static void
nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
struct nvc0_perfmon_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break;
case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break;
case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break;
}
cntr->base.clk = nv_rd32(priv, dom->addr + 0x070);
}
static void
nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
}
const struct nouveau_funcdom
nvc0_perfctr_func = {
.init = nvc0_perfctr_init,
.read = nvc0_perfctr_read,
.next = nvc0_perfctr_next,
};
int
nvc0_perfmon_fini(struct nouveau_object *object, bool suspend)
{
struct nvc0_perfmon_priv *priv = (void *)object;
nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
return nouveau_perfmon_fini(&priv->base, suspend);
}
static int
nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
u32 mask;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nvc0_perfmon_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nvc0_perfmon_hub);
if (ret)
return ret;
/* GPC */
mask = (1 << nv_rd32(priv, 0x022430)) - 1;
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nvc0_perfmon_gpc);
if (ret)
return ret;
/* PART */
mask = (1 << nv_rd32(priv, 0x022438)) - 1;
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nvc0_perfmon_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nvc0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};
drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h 0 → 100644
View file @ 4a15cdff
#ifndef __NVKM_PM_NVC0_H__
#define __NVKM_PM_NVC0_H__
#include "priv.h"
struct nvc0_perfmon_priv {
struct nouveau_perfmon base;
};
struct nvc0_perfmon_cntr {
struct nouveau_perfctr base;
};
extern const struct nouveau_funcdom nvc0_perfctr_func;
int nvc0_perfmon_fini(struct nouveau_object *, bool);
#endif
drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c 0 → 100644
View file @ 4a15cdff
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nve0_perfmon_hub[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
{ 0x27, "hub01_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub02_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub03_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
{ 0x03, "host_mmio_rd" },
{ 0x27, "hub04_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub05_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0xc0, (const struct nouveau_specsig[]) {
{ 0x74, "host_fb_rd3x" },
{ 0x75, "host_fb_rd3x_2" },
{ 0xa7, "hub06_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub07_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_perfmon_gpc[] = {
{ 0xe0, (const struct nouveau_specsig[]) {
{ 0xc7, "gpc00_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_perfmon_part[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "part00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "part01_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static int
nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
u32 mask;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
/* PDAEMON */
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_perfmon_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nve0_perfmon_hub);
if (ret)
return ret;
/* GPC */
mask = (1 << nv_rd32(priv, 0x022430)) - 1;
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nve0_perfmon_gpc);
if (ret)
return ret;
/* PART */
mask = (1 << nv_rd32(priv, 0x022438)) - 1;
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nve0_perfmon_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nve0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};
drivers/gpu/drm/nouveau/nv04_pm.c → drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c
View file @ 4a15cdff
/*
* Copyright 2010 Red Hat Inc.
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
......@@ -22,125 +22,50 @@
* Authors: Ben Skeggs
*/
#include <drm/drmP.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "dispnv04/hw.h"
#include "nouveau_pm.h"
#include "nvc0.h"
#include <subdev/bios/pll.h>
#include <subdev/clock.h>
#include <subdev/timer.h>
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
int
nv04_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
int ret;
ret = nouveau_hw_get_clock(dev, PLL_CORE);
if (ret < 0)
return ret;
perflvl->core = ret;
ret = nouveau_hw_get_clock(dev, PLL_MEMORY);
if (ret < 0)
return ret;
perflvl->memory = ret;
/*******************************************************************************
* PPM context
******************************************************************************/
return 0;
}
struct nv04_pm_clock {
struct nvbios_pll pll;
struct nouveau_pll_vals calc;
};
struct nv04_pm_state {
struct nv04_pm_clock core;
struct nv04_pm_clock memory;
};
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static int
calc_pll(struct drm_device *dev, u32 id, int khz, struct nv04_pm_clock *clk)
nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_bios *bios = nouveau_bios(device);
struct nouveau_clock *pclk = nouveau_clock(device);
struct nvc0_perfmon_priv *priv;
int ret;
ret = nvbios_pll_parse(bios, id, &clk->pll);
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = pclk->pll_calc(pclk, &clk->pll, khz, &clk->calc);
if (!ret)
return -EINVAL;
return 0;
}
void *
nv04_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
struct nv04_pm_state *info;
int ret;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
return ERR_PTR(-ENOMEM);
ret = calc_pll(dev, PLL_CORE, perflvl->core, &info->core);
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_perfmon_pwr);
if (ret)
goto error;
if (perflvl->memory) {
ret = calc_pll(dev, PLL_MEMORY, perflvl->memory, &info->memory);
if (ret)
goto error;
}
return info;
error:
kfree(info);
return ERR_PTR(ret);
}
static void
prog_pll(struct drm_device *dev, struct nv04_pm_clock *clk)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_clock *pclk = nouveau_clock(device);
u32 reg = clk->pll.reg;
/* thank the insane nouveau_hw_setpll() interface for this */
if (device->card_type >= NV_40)
reg += 4;
pclk->pll_prog(pclk, reg, &clk->calc);
}
int
nv04_pm_clocks_set(struct drm_device *dev, void *pre_state)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_timer *ptimer = nouveau_timer(device);
struct nv04_pm_state *state = pre_state;
prog_pll(dev, &state->core);
if (state->memory.pll.reg) {
prog_pll(dev, &state->memory);
if (device->card_type < NV_30) {
if (device->card_type == NV_20)
nv_mask(device, 0x1002c4, 0, 1 << 20);
/* Reset the DLLs */
nv_mask(device, 0x1002c0, 0, 1 << 8);
}
}
nv_ofuncs(ptimer)->init(nv_object(ptimer));
return ret;
kfree(state);
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
return 0;
}
struct nouveau_oclass
nvf0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xf0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvf0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};
drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h 0 → 100644
View file @ 4a15cdff
#ifndef __NVKM_PERFMON_PRIV_H__
#define __NVKM_PERFMON_PRIV_H__
#include <engine/perfmon.h>
struct nouveau_perfctr {
struct nouveau_object base;
struct list_head head;
struct nouveau_perfsig *signal[4];
int slot;
u32 logic_op;
u32 clk;
u32 ctr;
};
extern struct nouveau_oclass nouveau_perfmon_sclass[];
struct nouveau_perfctx {
struct nouveau_engctx base;
};
extern struct nouveau_oclass nouveau_perfmon_cclass;
struct nouveau_specsig {
u8 signal;
const char *name;
};
struct nouveau_perfsig {
const char *name;
};
struct nouveau_perfdom;
struct nouveau_perfctr *
nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *,
struct nouveau_perfdom **);
struct nouveau_specdom {
u16 signal_nr;
const struct nouveau_specsig *signal;
const struct nouveau_funcdom *func;
};
extern const struct nouveau_specdom nva3_perfmon_pwr[];
extern const struct nouveau_specdom nvc0_perfmon_pwr[];
extern const struct nouveau_specdom nve0_perfmon_pwr[];
struct nouveau_perfdom {
struct list_head head;
struct list_head list;
const struct nouveau_funcdom *func;
char name[32];
u32 addr;
u8 quad;
u32 signal_nr;
struct nouveau_perfsig signal[];
};
struct nouveau_funcdom {
void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *);
};
int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32,
u32, u32, u32, const struct nouveau_specdom *);
#define nouveau_perfmon_create(p,e,o,d) \
nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_perfmon_dtor(p) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_dtor(nv_object(c)); \
})
#define nouveau_perfmon_init(p) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_init(nv_object(c)); \
})
#define nouveau_perfmon_fini(p,s) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_fini(nv_object(c), (s)); \
})
int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void _nouveau_perfmon_dtor(struct nouveau_object *);
int _nouveau_perfmon_init(struct nouveau_object *);
int _nouveau_perfmon_fini(struct nouveau_object *, bool);
#endif
drivers/gpu/drm/nouveau/core/engine/software/nv04.c
View file @ 4a15cdff
......@@ -135,8 +135,8 @@ nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv04_software_oclass = {
struct nouveau_oclass *
nv04_software_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(SW, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_software_ctor,
......
drivers/gpu/drm/nouveau/core/engine/software/nv10.c
View file @ 4a15cdff
......@@ -117,8 +117,8 @@ nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv10_software_oclass = {
struct nouveau_oclass *
nv10_software_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(SW, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv10_software_ctor,
......
drivers/gpu/drm/nouveau/core/engine/software/nv50.h 0 → 100644
View file @ 4a15cdff
#ifndef __NVKM_SW_NV50_H__
#define __NVKM_SW_NV50_H__
#include <engine/software.h>
struct nv50_software_oclass {
struct nouveau_oclass base;
struct nouveau_oclass *cclass;
struct nouveau_oclass *sclass;
};
struct nv50_software_priv {
struct nouveau_software base;
};
int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
struct nv50_software_cclass {
struct nouveau_oclass base;
int (*vblank)(void *, int);
};
struct nv50_software_chan {
struct nouveau_software_chan base;
struct {
struct nouveau_eventh **event;
int nr_event;
u32 channel;
u32 ctxdma;
u64 offset;
u32 value;
} vblank;
};
int nv50_software_context_ctor(struct nouveau_object *,
struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nv50_software_context_dtor(struct nouveau_object *);
int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32);
#endif
drivers/gpu/drm/nouveau/core/include/core/class.h
View file @ 4a15cdff
......@@ -22,7 +22,7 @@
#define NV_DEVICE_DISABLE_PPP 0x0000004000000000ULL
#define NV_DEVICE_DISABLE_COPY0 0x0000008000000000ULL
#define NV_DEVICE_DISABLE_COPY1 0x0000010000000000ULL
#define NV_DEVICE_DISABLE_UNK1C1 0x0000020000000000ULL
#define NV_DEVICE_DISABLE_VIC 0x0000020000000000ULL
#define NV_DEVICE_DISABLE_VENC 0x0000040000000000ULL
struct nv_device_class {
......@@ -98,6 +98,77 @@ struct nv_dma_class {
u32 conf0;
};
/* Perfmon counter class
*
* XXXX: NV_PERFCTR
*/
#define NV_PERFCTR_CLASS 0x0000ffff
#define NV_PERFCTR_QUERY 0x00000000
#define NV_PERFCTR_SAMPLE 0x00000001
#define NV_PERFCTR_READ 0x00000002
struct nv_perfctr_class {
u16 logic_op;
struct {
char __user *name; /*XXX: use cfu when exposed to userspace */
u32 size;
} signal[4];
};
struct nv_perfctr_query {
u32 iter;
u32 size;
char __user *name; /*XXX: use ctu when exposed to userspace */
};
struct nv_perfctr_sample {
};
struct nv_perfctr_read {
u32 ctr;
u32 clk;
};
/* Device control class
*
* XXXX: NV_CONTROL
*/
#define NV_CONTROL_CLASS 0x0000fffe
#define NV_CONTROL_PSTATE_INFO 0x00000000
#define NV_CONTROL_PSTATE_INFO_USTATE_DISABLE (-1)
#define NV_CONTROL_PSTATE_INFO_USTATE_PERFMON (-2)
#define NV_CONTROL_PSTATE_INFO_PSTATE_UNKNOWN (-1)
#define NV_CONTROL_PSTATE_INFO_PSTATE_PERFMON (-2)
#define NV_CONTROL_PSTATE_ATTR 0x00000001
#define NV_CONTROL_PSTATE_ATTR_STATE_CURRENT (-1)
#define NV_CONTROL_PSTATE_USER 0x00000002
#define NV_CONTROL_PSTATE_USER_STATE_UNKNOWN (-1)
#define NV_CONTROL_PSTATE_USER_STATE_PERFMON (-2)
struct nv_control_pstate_info {
u32 count; /* out: number of power states */
s32 ustate; /* out: current target pstate index */
u32 pstate; /* out: current pstate index */
};
struct nv_control_pstate_attr {
s32 state; /* in: index of pstate to query
* out: pstate identifier
*/
u32 index; /* in: index of attribute to query
* out: index of next attribute, or 0 if no more
*/
char name[32];
char unit[16];
u32 min;
u32 max;
};
struct nv_control_pstate_user {
s32 state; /* in: pstate identifier */
};
/* DMA FIFO channel classes
*
* 006b: NV03_CHANNEL_DMA
......
drivers/gpu/drm/nouveau/core/include/engine/perfmon.h 0 → 100644
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drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h 0 → 100644
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drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h 0 → 100644
View file @ 4a15cdff
#ifndef __NVBIOS_TIMING_H__
#define __NVBIOS_TIMING_H__
u16 nvbios_timing_table(struct nouveau_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_timing_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
#endif
drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h 0 → 100644
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drivers/gpu/drm/nouveau/core/include/subdev/pwr.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bios/boost.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bios/timing.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bios/volt.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/clock/base.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/clock/seq.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/base.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/volt/base.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c 0 → 100644
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drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c 0 → 100644
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