Commit 4ad2c061 authored by Magnus Damm's avatar Magnus Damm Committed by Rafael J. Wysocki

sh: sh2a sh_clk_ops rename

Convert sh2a SoCs to use sh_clk_ops.
Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarRafael J. Wysocki <rjw@sisk.pl>
parent 71984236
...@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk) ...@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
} }
static struct clk_ops sh7201_master_clk_ops = { static struct sh_clk_ops sh7201_master_clk_ops = {
.init = master_clk_init, .init = master_clk_init,
}; };
...@@ -40,7 +40,7 @@ static unsigned long module_clk_recalc(struct clk *clk) ...@@ -40,7 +40,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx];
} }
static struct clk_ops sh7201_module_clk_ops = { static struct sh_clk_ops sh7201_module_clk_ops = {
.recalc = module_clk_recalc, .recalc = module_clk_recalc,
}; };
...@@ -50,7 +50,7 @@ static unsigned long bus_clk_recalc(struct clk *clk) ...@@ -50,7 +50,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx];
} }
static struct clk_ops sh7201_bus_clk_ops = { static struct sh_clk_ops sh7201_bus_clk_ops = {
.recalc = bus_clk_recalc, .recalc = bus_clk_recalc,
}; };
...@@ -60,18 +60,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk) ...@@ -60,18 +60,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx]; return clk->parent->rate / ifc_divisors[idx];
} }
static struct clk_ops sh7201_cpu_clk_ops = { static struct sh_clk_ops sh7201_cpu_clk_ops = {
.recalc = cpu_clk_recalc, .recalc = cpu_clk_recalc,
}; };
static struct clk_ops *sh7201_clk_ops[] = { static struct sh_clk_ops *sh7201_clk_ops[] = {
&sh7201_master_clk_ops, &sh7201_master_clk_ops,
&sh7201_module_clk_ops, &sh7201_module_clk_ops,
&sh7201_bus_clk_ops, &sh7201_bus_clk_ops,
&sh7201_cpu_clk_ops, &sh7201_cpu_clk_ops,
}; };
void __init arch_init_clk_ops(struct clk_ops **ops, int idx) void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{ {
if (test_mode_pin(MODE_PIN1 | MODE_PIN0)) if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
pll2_mult = 1; pll2_mult = 1;
......
...@@ -32,7 +32,7 @@ static void master_clk_init(struct clk *clk) ...@@ -32,7 +32,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
} }
static struct clk_ops sh7203_master_clk_ops = { static struct sh_clk_ops sh7203_master_clk_ops = {
.init = master_clk_init, .init = master_clk_init,
}; };
...@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk) ...@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx];
} }
static struct clk_ops sh7203_module_clk_ops = { static struct sh_clk_ops sh7203_module_clk_ops = {
.recalc = module_clk_recalc, .recalc = module_clk_recalc,
}; };
...@@ -52,22 +52,22 @@ static unsigned long bus_clk_recalc(struct clk *clk) ...@@ -52,22 +52,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx-2]; return clk->parent->rate / pfc_divisors[idx-2];
} }
static struct clk_ops sh7203_bus_clk_ops = { static struct sh_clk_ops sh7203_bus_clk_ops = {
.recalc = bus_clk_recalc, .recalc = bus_clk_recalc,
}; };
static struct clk_ops sh7203_cpu_clk_ops = { static struct sh_clk_ops sh7203_cpu_clk_ops = {
.recalc = followparent_recalc, .recalc = followparent_recalc,
}; };
static struct clk_ops *sh7203_clk_ops[] = { static struct sh_clk_ops *sh7203_clk_ops[] = {
&sh7203_master_clk_ops, &sh7203_master_clk_ops,
&sh7203_module_clk_ops, &sh7203_module_clk_ops,
&sh7203_bus_clk_ops, &sh7203_bus_clk_ops,
&sh7203_cpu_clk_ops, &sh7203_cpu_clk_ops,
}; };
void __init arch_init_clk_ops(struct clk_ops **ops, int idx) void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{ {
if (test_mode_pin(MODE_PIN1)) if (test_mode_pin(MODE_PIN1))
pll2_mult = 4; pll2_mult = 4;
......
...@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk) ...@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
} }
static struct clk_ops sh7206_master_clk_ops = { static struct sh_clk_ops sh7206_master_clk_ops = {
.init = master_clk_init, .init = master_clk_init,
}; };
...@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk) ...@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
return clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx];
} }
static struct clk_ops sh7206_module_clk_ops = { static struct sh_clk_ops sh7206_module_clk_ops = {
.recalc = module_clk_recalc, .recalc = module_clk_recalc,
}; };
...@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk) ...@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
} }
static struct clk_ops sh7206_bus_clk_ops = { static struct sh_clk_ops sh7206_bus_clk_ops = {
.recalc = bus_clk_recalc, .recalc = bus_clk_recalc,
}; };
...@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk) ...@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
return clk->parent->rate / ifc_divisors[idx]; return clk->parent->rate / ifc_divisors[idx];
} }
static struct clk_ops sh7206_cpu_clk_ops = { static struct sh_clk_ops sh7206_cpu_clk_ops = {
.recalc = cpu_clk_recalc, .recalc = cpu_clk_recalc,
}; };
static struct clk_ops *sh7206_clk_ops[] = { static struct sh_clk_ops *sh7206_clk_ops[] = {
&sh7206_master_clk_ops, &sh7206_master_clk_ops,
&sh7206_module_clk_ops, &sh7206_module_clk_ops,
&sh7206_bus_clk_ops, &sh7206_bus_clk_ops,
&sh7206_cpu_clk_ops, &sh7206_cpu_clk_ops,
}; };
void __init arch_init_clk_ops(struct clk_ops **ops, int idx) void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
{ {
if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0)) if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
pll2_mult = 1; pll2_mult = 1;
......
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