Commit 4b5d95b3 authored by Éric Piel's avatar Éric Piel Committed by Linus Torvalds

lis3: fix show rate for 8 bits chips

Originally the driver was only targeted to 12bits sensors.  When support
for 8bits sensors was added, some slight difference in the registers were
overlooked.  This should fix it, both for initialization, and for
displaying the rate.
Reported-by: default avatarKalhan Trisal <kalhan.trisal@intel.com>
Reported-by: default avatarChristoph Plattner <christoph.plattner@gmx.at>
Tested-by: default avatarChristoph Plattner <christoph.plattner@gmx.at>
Tested-by: default avatarSamu Onkalo <samu.p.onkalo@nokia.com>
Signed-off-by: default avatarÉric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: default avatarSamu Onkalo <samu.p.onkalo@nokia.com>
Cc: Pavel Machek <pavel@ucw.cz>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent bc62c147
...@@ -127,12 +127,14 @@ void lis3lv02d_poweron(struct lis3lv02d *lis3) ...@@ -127,12 +127,14 @@ void lis3lv02d_poweron(struct lis3lv02d *lis3)
/* /*
* Common configuration * Common configuration
* BDU: LSB and MSB values are not updated until both have been read. * BDU: (12 bits sensors only) LSB and MSB values are not updated until
* So the value read will always be correct. * both have been read. So the value read will always be correct.
*/ */
lis3->read(lis3, CTRL_REG2, &reg); if (lis3->whoami == WAI_12B) {
reg |= CTRL2_BDU; lis3->read(lis3, CTRL_REG2, &reg);
lis3->write(lis3, CTRL_REG2, reg); reg |= CTRL2_BDU;
lis3->write(lis3, CTRL_REG2, reg);
}
} }
EXPORT_SYMBOL_GPL(lis3lv02d_poweron); EXPORT_SYMBOL_GPL(lis3lv02d_poweron);
...@@ -363,7 +365,8 @@ static ssize_t lis3lv02d_calibrate_store(struct device *dev, ...@@ -363,7 +365,8 @@ static ssize_t lis3lv02d_calibrate_store(struct device *dev,
} }
/* conversion btw sampling rate and the register values */ /* conversion btw sampling rate and the register values */
static int lis3lv02dl_df_val[4] = {40, 160, 640, 2560}; static int lis3_12_rates[4] = {40, 160, 640, 2560};
static int lis3_8_rates[2] = {100, 400};
static ssize_t lis3lv02d_rate_show(struct device *dev, static ssize_t lis3lv02d_rate_show(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
...@@ -371,8 +374,13 @@ static ssize_t lis3lv02d_rate_show(struct device *dev, ...@@ -371,8 +374,13 @@ static ssize_t lis3lv02d_rate_show(struct device *dev,
int val; int val;
lis3_dev.read(&lis3_dev, CTRL_REG1, &ctrl); lis3_dev.read(&lis3_dev, CTRL_REG1, &ctrl);
val = (ctrl & (CTRL1_DF0 | CTRL1_DF1)) >> 4;
return sprintf(buf, "%d\n", lis3lv02dl_df_val[val]); if (lis3_dev.whoami == WAI_12B)
val = lis3_12_rates[(ctrl & (CTRL1_DF0 | CTRL1_DF1)) >> 4];
else
val = lis3_8_rates[(ctrl & CTRL1_DR) >> 7];
return sprintf(buf, "%d\n", val);
} }
static DEVICE_ATTR(position, S_IRUGO, lis3lv02d_position_show, NULL); static DEVICE_ATTR(position, S_IRUGO, lis3lv02d_position_show, NULL);
......
...@@ -107,6 +107,7 @@ enum lis3lv02d_ctrl1 { ...@@ -107,6 +107,7 @@ enum lis3lv02d_ctrl1 {
CTRL1_DF1 = 0x20, CTRL1_DF1 = 0x20,
CTRL1_PD0 = 0x40, CTRL1_PD0 = 0x40,
CTRL1_PD1 = 0x80, CTRL1_PD1 = 0x80,
CTRL1_DR = 0x80, /* Data rate on 8 bits */
}; };
enum lis3lv02d_ctrl2 { enum lis3lv02d_ctrl2 {
CTRL2_DAS = 0x01, CTRL2_DAS = 0x01,
......
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