Commit 4d55b0dd authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher

drm/amd/display: Add DCN3 CLK_MGR

Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent be547111
...@@ -97,3 +97,13 @@ AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DC ...@@ -97,3 +97,13 @@ AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DC
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
endif endif
ifdef CONFIG_DRM_AMD_DC_DCN3_0
###############################################################################
# DCN30
###############################################################################
CLK_MGR_DCN30 = dcn30_clk_mgr.o dcn30_clk_mgr_smu_msg.o
AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
endif
...@@ -38,6 +38,9 @@ ...@@ -38,6 +38,9 @@
#include "dcn10/rv2_clk_mgr.h" #include "dcn10/rv2_clk_mgr.h"
#include "dcn20/dcn20_clk_mgr.h" #include "dcn20/dcn20_clk_mgr.h"
#include "dcn21/rn_clk_mgr.h" #include "dcn21/rn_clk_mgr.h"
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#include "dcn30/dcn30_clk_mgr.h"
#endif
int clk_mgr_helper_get_active_display_cnt( int clk_mgr_helper_get_active_display_cnt(
...@@ -169,6 +172,15 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p ...@@ -169,6 +172,15 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
break; break;
case FAMILY_NV: case FAMILY_NV:
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
/* TODO: to add SIENNA_CICHLID clk_mgr support, once CLK IP header files are available,
* for now use DCN3AG clk mgr.
*/
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break;
}
#endif
dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break; break;
#endif /* Family RV and NV*/ #endif /* Family RV and NV*/
...@@ -184,6 +196,16 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p ...@@ -184,6 +196,16 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
{ {
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
switch (clk_mgr_base->ctx->asic_id.chip_family) {
case FAMILY_NV:
if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
dcn3_clk_mgr_destroy(clk_mgr);
break;
}
}
#endif
kfree(clk_mgr); kfree(clk_mgr);
} }
......
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
// TEMPORARY until this exists in the proper location
#ifndef DALSMC_H
#define DALSMC_H
#define DALSMC_VERSION 0x1
// SMU Response Codes:
#define DALSMC_Result_OK 0x1
#define DALSMC_Result_Failed 0xFF
#define DALSMC_Result_UnknownCmd 0xFE
#define DALSMC_Result_CmdRejectedPrereq 0xFD
#define DALSMC_Result_CmdRejectedBusy 0xFC
// Message Definitions:
#define DALSMC_MSG_TestMessage 0x1
#define DALSMC_MSG_GetSmuVersion 0x2
#define DALSMC_MSG_GetDriverIfVersion 0x3
#define DALSMC_MSG_GetMsgHeaderVersion 0x4
#define DALSMC_MSG_SetDalDramAddrHigh 0x5
#define DALSMC_MSG_SetDalDramAddrLow 0x6
#define DALSMC_MSG_TransferTableSmu2Dram 0x7
#define DALSMC_MSG_TransferTableDram2Smu 0x8
#define DALSMC_MSG_SetHardMinByFreq 0x9
#define DALSMC_MSG_SetHardMaxByFreq 0xA
#define DALSMC_MSG_GetDpmFreqByIndex 0xB
#define DALSMC_MSG_GetDcModeMaxDpmFreq 0xC
#define DALSMC_MSG_SetMinDeepSleepDcefclk 0xD
#define DALSMC_MSG_NumOfDisplays 0xE
#define DALSMC_MSG_SetExternalClientDfCstateAllow 0x10
#define DALSMC_MSG_BacoAudioD3PME 0x11
#define DALSMC_Message_Count 0x12
#endif
This diff is collapsed.
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DCN30_CLK_MGR_H__
#define __DCN30_CLK_MGR_H__
void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
void dcn3_clk_mgr_construct(struct dc_context *ctx,
struct clk_mgr_internal *clk_mgr,
struct pp_smu_funcs *pp_smu,
struct dccg *dccg);
void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
#endif //__DCN30_CLK_MGR_H__
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <linux/delay.h>
#include "dcn30_clk_mgr_smu_msg.h"
#include "clk_mgr_internal.h"
#include "reg_helper.h"
#include "dalsmc.h"
#define mmDAL_MSG_REG 0x1628A
#define mmDAL_ARG_REG 0x16273
#define mmDAL_RESP_REG 0x16274
#define REG(reg_name) \
mm ## reg_name
/*
* Function to be used instead of REG_WAIT macro because the wait ends when
* the register is NOT EQUAL to zero, and because the translation in msg_if.h
* won't work with REG_WAIT.
*/
static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
{
uint32_t reg = 0;
do {
reg = REG_READ(DAL_RESP_REG);
if (reg)
break;
if (delay_us >= 1000)
msleep(delay_us/1000);
else if (delay_us > 0)
udelay(delay_us);
} while (max_retries--);
/* handle DALSMC_Result_CmdRejectedBusy? */
/* Log? */
return reg;
}
static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
{
/* Wait for response register to be ready */
dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
/* Clear response register */
REG_WRITE(DAL_RESP_REG, 0);
/* Set the parameter register for the SMU message */
REG_WRITE(DAL_ARG_REG, param_in);
/* Trigger the message transaction by writing the message ID */
REG_WRITE(DAL_MSG_REG, msg_id);
/* Wait for response */
if (dcn30_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
if (param_out)
*param_out = REG_READ(DAL_ARG_REG);
return true;
}
return false;
}
/* Test message should return input + 1 */
bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)
{
uint32_t response = 0;
if (dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_TestMessage, input, &response))
if (response == input + 1)
return true;
return false;
}
bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
{
if (dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_GetSmuVersion, 0, version))
return true;
return false;
}
/* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */
bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
{
uint32_t response = 0;
if (dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_GetDriverIfVersion, 0, &response))
if (response == SMU11_DRIVER_IF_VERSION)
return true;
return false;
}
/* Message output should match DALSMC_VERSION in dalsmc.h */
bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
{
uint32_t response = 0;
if (dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_GetMsgHeaderVersion, 0, &response))
if (response == DALSMC_VERSION)
return true;
return false;
}
void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);
}
void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);
}
void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_TransferTableSmu2Dram, TABLE_WATERMARKS, NULL);
}
void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
}
/* Returns the actual frequency that was set in MHz, 0 on failure */
unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz)
{
uint32_t response = 0;
/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
uint32_t param = (clk << 16) | freq_mhz;
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetHardMinByFreq, param, &response);
return response;
}
/* Returns the actual frequency that was set in MHz, 0 on failure */
unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz)
{
uint32_t response = 0;
/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
uint32_t param = (clk << 16) | freq_mhz;
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetHardMaxByFreq, param, &response);
return response;
}
/*
* Frequency in MHz returned in lower 16 bits for valid DPM level
*
* Call with dpm_level = 0xFF to query features, return value will be:
* Bits 7:0 - number of DPM levels
* Bit 28 - 1 = auto DPM on
* Bit 29 - 1 = sweep DPM on
* Bit 30 - 1 = forced DPM on
* Bit 31 - 0 = discrete, 1 = fine-grained
*
* With fine-grained DPM, only min and max frequencies will be reported
*
* Returns 0 on failure
*/
unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint8_t dpm_level)
{
uint32_t response = 0;
/* bits 23:16 for clock type, lower 8 bits for DPM level */
uint32_t param = (clk << 16) | dpm_level;
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_GetDpmFreqByIndex, param, &response);
return response;
}
/* Returns the max DPM frequency in DC mode in MHz, 0 on failure */
unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
{
uint32_t response = 0;
/* bits 23:16 for clock type */
uint32_t param = clk << 16;
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response);
return response;
}
void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetMinDeepSleepDcefclk, freq_mhz, NULL);
}
void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_NumOfDisplays, num_displays, NULL);
}
void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetExternalClientDfCstateAllow, enable ? 1 : 0, NULL);
}
void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
{
dcn30_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_BacoAudioD3PME, 0, NULL);
}
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_
#define DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_
#include "core_types.h"
#define SMU11_DRIVER_IF_VERSION 0x1F
typedef enum {
PPCLK_GFXCLK = 0,
PPCLK_SOCCLK,
PPCLK_UCLK,
PPCLK_FCLK,
PPCLK_DCLK_0,
PPCLK_VCLK_0,
PPCLK_DCLK_1,
PPCLK_VCLK_1,
PPCLK_DCEFCLK,
PPCLK_DISPCLK,
PPCLK_PIXCLK,
PPCLK_PHYCLK,
PPCLK_DTBCLK,
PPCLK_COUNT,
} PPCLK_e;
typedef struct {
uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
uint16_t MinUclk;
uint16_t MaxUclk;
uint8_t WmSetting;
uint8_t Flags;
uint8_t Padding[2];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
typedef enum {
WM_SOCCLK = 0,
WM_DCEFCLK,
WM_COUNT,
} WM_CLOCK_e;
typedef enum {
WATERMARKS_CLOCK_RANGE = 0,
WATERMARKS_DUMMY_PSTATE,
WATERMARKS_COUNT,
} WATERMARKS_FLAGS_e;
typedef struct {
// Watermarks
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
} Watermarks_t;
typedef struct {
Watermarks_t Watermarks;
uint32_t MmHubPadding[8]; // SMU internal use
} WatermarksExternal_t;
#define TABLE_WATERMARKS 1
struct clk_mgr_internal;
bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz);
unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz);
unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint8_t dpm_level);
unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk);
void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);
void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable);
void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
#endif /* DAL_DC_DCN30_CLK_MGR_SMU_MSG_H_ */
...@@ -729,6 +729,9 @@ static bool dc_construct(struct dc *dc, ...@@ -729,6 +729,9 @@ static bool dc_construct(struct dc *dc,
dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
if (!dc->clk_mgr) if (!dc->clk_mgr)
goto fail; goto fail;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
#endif
if (dc->res_pool->funcs->update_bw_bounding_box) if (dc->res_pool->funcs->update_bw_bounding_box)
dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
...@@ -2819,3 +2822,51 @@ void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_ ...@@ -2819,3 +2822,51 @@ void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_
if (dc->hwss.get_clock) if (dc->hwss.get_clock)
dc->hwss.get_clock(dc, clock_type, clock_cfg); dc->hwss.get_clock(dc, clock_type, clock_cfg);
} }
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void dc_allow_idle_optimizations(struct dc *dc, bool allow)
{
if (dc->debug.disable_idle_power_optimizations)
return;
if (allow == dc->idle_optimizations_allowed)
return;
if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
dc->idle_optimizations_allowed = allow;
}
/*
* blank all streams, and set min and max memory clock to
* lowest and highest DPM level, respectively
*/
void dc_unlock_memory_clock_frequency(struct dc *dc)
{
unsigned int i;
for (i = 0; i < MAX_PIPES; i++)
if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
}
/*
* set min memory clock to the min required for current mode,
* max to maxDPM, and unblank streams
*/
void dc_lock_memory_clock_frequency(struct dc *dc)
{
unsigned int i;
dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
for (i = 0; i < MAX_PIPES; i++)
if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
}
#endif
...@@ -243,6 +243,9 @@ bool dc_stream_set_cursor_attributes( ...@@ -243,6 +243,9 @@ bool dc_stream_set_cursor_attributes(
struct dc *dc; struct dc *dc;
struct resource_context *res_ctx; struct resource_context *res_ctx;
struct pipe_ctx *pipe_to_program = NULL; struct pipe_ctx *pipe_to_program = NULL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool reset_idle_optimizations = false;
#endif
if (NULL == stream) { if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n"); dm_error("DC: dc_stream is NULL!\n");
...@@ -262,6 +265,15 @@ bool dc_stream_set_cursor_attributes( ...@@ -262,6 +265,15 @@ bool dc_stream_set_cursor_attributes(
res_ctx = &dc->current_state->res_ctx; res_ctx = &dc->current_state->res_ctx;
stream->cursor_attributes = *attributes; stream->cursor_attributes = *attributes;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/* disable idle optimizations while updating cursor */
if (dc->idle_optimizations_allowed) {
dc->hwss.apply_idle_power_optimizations(dc, false);
reset_idle_optimizations = true;
}
#endif
for (i = 0; i < MAX_PIPES; i++) { for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
...@@ -281,6 +293,12 @@ bool dc_stream_set_cursor_attributes( ...@@ -281,6 +293,12 @@ bool dc_stream_set_cursor_attributes(
if (pipe_to_program) if (pipe_to_program)
dc->hwss.cursor_lock(dc, pipe_to_program, false); dc->hwss.cursor_lock(dc, pipe_to_program, false);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/* re-enable idle optimizations if necessary */
if (reset_idle_optimizations)
dc->hwss.apply_idle_power_optimizations(dc, true);
#endif
return true; return true;
} }
...@@ -292,6 +310,9 @@ bool dc_stream_set_cursor_position( ...@@ -292,6 +310,9 @@ bool dc_stream_set_cursor_position(
struct dc *dc; struct dc *dc;
struct resource_context *res_ctx; struct resource_context *res_ctx;
struct pipe_ctx *pipe_to_program = NULL; struct pipe_ctx *pipe_to_program = NULL;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool reset_idle_optimizations = false;
#endif
if (NULL == stream) { if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n"); dm_error("DC: dc_stream is NULL!\n");
...@@ -305,6 +326,16 @@ bool dc_stream_set_cursor_position( ...@@ -305,6 +326,16 @@ bool dc_stream_set_cursor_position(
dc = stream->ctx->dc; dc = stream->ctx->dc;
res_ctx = &dc->current_state->res_ctx; res_ctx = &dc->current_state->res_ctx;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/* disable idle optimizations if enabling cursor */
if (dc->idle_optimizations_allowed &&
!stream->cursor_position.enable && position->enable) {
dc->hwss.apply_idle_power_optimizations(dc, false);
reset_idle_optimizations = true;
}
#endif
stream->cursor_position = *position; stream->cursor_position = *position;
for (i = 0; i < MAX_PIPES; i++) { for (i = 0; i < MAX_PIPES; i++) {
...@@ -328,6 +359,12 @@ bool dc_stream_set_cursor_position( ...@@ -328,6 +359,12 @@ bool dc_stream_set_cursor_position(
if (pipe_to_program) if (pipe_to_program)
dc->hwss.cursor_lock(dc, pipe_to_program, false); dc->hwss.cursor_lock(dc, pipe_to_program, false);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/* re-enable idle optimizations if necessary */
if (reset_idle_optimizations)
dc->hwss.apply_idle_power_optimizations(dc, true);
#endif
return true; return true;
} }
......
...@@ -459,6 +459,9 @@ struct dc_debug_options { ...@@ -459,6 +459,9 @@ struct dc_debug_options {
bool disable_tri_buf; bool disable_tri_buf;
bool dmub_offload_enabled; bool dmub_offload_enabled;
bool dmcub_emulation; bool dmcub_emulation;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool disable_idle_power_optimizations;
#endif
bool dmub_command_table; /* for testing only */ bool dmub_command_table; /* for testing only */
struct dc_bw_validation_profile bw_val_profile; struct dc_bw_validation_profile bw_val_profile;
bool disable_fec; bool disable_fec;
...@@ -572,6 +575,9 @@ struct dc { ...@@ -572,6 +575,9 @@ struct dc {
/* Require to optimize clocks and bandwidth for added/removed planes */ /* Require to optimize clocks and bandwidth for added/removed planes */
bool optimized_required; bool optimized_required;
bool wm_optimized_required; bool wm_optimized_required;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool idle_optimizations_allowed;
#endif
/* Require to maintain clocks and bandwidth for UEFI enabled HW */ /* Require to maintain clocks and bandwidth for UEFI enabled HW */
int optimize_seamless_boot_streams; int optimize_seamless_boot_streams;
...@@ -628,6 +634,9 @@ struct dc_init_data { ...@@ -628,6 +634,9 @@ struct dc_init_data {
*/ */
const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
struct dpcd_vendor_signature vendor_signature; struct dpcd_vendor_signature vendor_signature;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool force_smu_not_present;
#endif
}; };
struct dc_callback_init { struct dc_callback_init {
...@@ -1198,6 +1207,23 @@ bool dc_is_dmcu_initialized(struct dc *dc); ...@@ -1198,6 +1207,23 @@ bool dc_is_dmcu_initialized(struct dc *dc);
enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void dc_allow_idle_optimizations(struct dc *dc, bool allow);
/*
* blank all streams, and set min and max memory clock to
* lowest and highest DPM level, respectively
*/
void dc_unlock_memory_clock_frequency(struct dc *dc);
/*
* set min memory clock to the min required for current mode,
* max to maxDPM, and unblank streams
*/
void dc_lock_memory_clock_frequency(struct dc *dc);
#endif
/******************************************************************************* /*******************************************************************************
* DSC Interfaces * DSC Interfaces
******************************************************************************/ ******************************************************************************/
......
...@@ -1004,16 +1004,58 @@ static bool get_pixel_clk_frequency_100hz( ...@@ -1004,16 +1004,58 @@ static bool get_pixel_clk_frequency_100hz(
return false; return false;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
struct pixel_rate_range_table_entry { const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
unsigned int range_min_khz; // /1.001 rates
unsigned int range_max_khz; {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
unsigned int target_pixel_rate_khz; {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
unsigned short mult_factor; {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
unsigned short div_factor; {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
{148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
{167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
{222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
{257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429
{296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033
{342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857
{395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6
{409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091
{445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055
{467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325
{519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231
{525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974
{545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455
{593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066
{623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377
{692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308
{701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987
{791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209
{890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099
{1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131
// *1.001 rates
{27020, 27030, 27000, 1001, 1000}, //27Mhz
{54050, 54060, 54000, 1001, 1000}, //54Mhz
{108100, 108110, 108000, 1001, 1000},//108Mhz
}; };
const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
unsigned int pixel_rate_khz)
{
int i;
for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {
return e;
}
}
return NULL;
}
#endif
static bool dcn20_program_pix_clk( static bool dcn20_program_pix_clk(
struct clock_source *clock_source, struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params, struct pixel_clk_params *pix_clk_params,
...@@ -1031,6 +1073,85 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = { ...@@ -1031,6 +1073,85 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = {
.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
}; };
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
static bool dcn3_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
struct pll_settings *pll_settings)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
const struct pixel_rate_range_table_entry *e =
look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
// For these signal types Driver to program DP_DTO without calling VBIOS Command table
if (dc_is_dp_signal(pix_clk_params->signal_type)) {
if (e) {
/* Set DTO values: phase = target clock, modulo = reference clock*/
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
} else {
/* Set DTO values: phase = target clock, modulo = reference clock*/
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
}
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
} else
// For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
return true;
}
static uint32_t dcn3_get_pix_clk_dividers(
struct clock_source *cs,
struct pixel_clk_params *pix_clk_params,
struct pll_settings *pll_settings)
{
unsigned long long actual_pix_clk_100Hz = pix_clk_params->requested_pix_clk_100hz;
struct dce110_clk_src *clk_src;
clk_src = TO_DCE110_CLK_SRC(cs);
DC_LOGGER_INIT();
if (pix_clk_params == NULL || pll_settings == NULL
|| pix_clk_params->requested_pix_clk_100hz == 0) {
DC_LOG_ERROR(
"%s: Invalid parameters!!\n", __func__);
return -1;
}
memset(pll_settings, 0, sizeof(*pll_settings));
/* Adjust for HDMI Type A deep color */
if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
switch (pix_clk_params->color_depth) {
case COLOR_DEPTH_101010:
actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
break;
case COLOR_DEPTH_121212:
actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
break;
case COLOR_DEPTH_161616:
actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
break;
default:
break;
}
}
pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
return 0;
}
static const struct clock_source_funcs dcn3_clk_src_funcs = {
.cs_power_down = dce110_clock_source_power_down,
.program_pix_clk = dcn3_program_pix_clk,
.get_pix_clk_dividers = dcn3_get_pix_clk_dividers
};
#endif
/*****************************************/ /*****************************************/
/* Constructor */ /* Constructor */
/*****************************************/ /*****************************************/
...@@ -1415,3 +1536,21 @@ bool dcn20_clk_src_construct( ...@@ -1415,3 +1536,21 @@ bool dcn20_clk_src_construct(
return ret; return ret;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool dcn3_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask)
{
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
clk_src->base.funcs = &dcn3_clk_src_funcs;
return ret;
}
#endif
...@@ -91,6 +91,23 @@ ...@@ -91,6 +91,23 @@
SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII(PIXEL_RATE_CNTL, OTG, 2),\
SRII(PIXEL_RATE_CNTL, OTG, 3) SRII(PIXEL_RATE_CNTL, OTG, 3)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 2),\
SRII(PHASE, DP_DTO, 3),\
SRII(MODULO, DP_DTO, 0),\
SRII(MODULO, DP_DTO, 1),\
SRII(MODULO, DP_DTO, 2),\
SRII(MODULO, DP_DTO, 3),\
SRII(PIXEL_RATE_CNTL, OTG, 0),\
SRII(PIXEL_RATE_CNTL, OTG, 1),\
SRII(PIXEL_RATE_CNTL, OTG, 2),\
SRII(PIXEL_RATE_CNTL, OTG, 3)
#endif
#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
...@@ -204,4 +221,29 @@ bool dcn20_clk_src_construct( ...@@ -204,4 +221,29 @@ bool dcn20_clk_src_construct(
const struct dce110_clk_src_shift *cs_shift, const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask); const struct dce110_clk_src_mask *cs_mask);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool dcn3_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask);
#endif
/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
struct pixel_rate_range_table_entry {
unsigned int range_min_khz;
unsigned int range_max_khz;
unsigned int target_pixel_rate_khz;
unsigned short mult_factor;
unsigned short div_factor;
};
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
unsigned int pixel_rate_khz);
#endif
#endif #endif
...@@ -43,6 +43,25 @@ ...@@ -43,6 +43,25 @@
#define DCN_MINIMUM_DISPCLK_Khz 100000 #define DCN_MINIMUM_DISPCLK_Khz 100000
#define DCN_MINIMUM_DPPCLK_Khz 100000 #define DCN_MINIMUM_DPPCLK_Khz 100000
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct dcn3_clk_internal {
int dummy;
/*TODO:
uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow
uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
*/
};
#endif
/* Will these bw structures be ASIC specific? */ /* Will these bw structures be ASIC specific? */
#define MAX_NUM_DPM_LVL 8 #define MAX_NUM_DPM_LVL 8
...@@ -55,6 +74,12 @@ struct clk_limit_table_entry { ...@@ -55,6 +74,12 @@ struct clk_limit_table_entry {
unsigned int fclk_mhz; unsigned int fclk_mhz;
unsigned int memclk_mhz; unsigned int memclk_mhz;
unsigned int socclk_mhz; unsigned int socclk_mhz;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
unsigned int dtbclk_mhz;
unsigned int dispclk_mhz;
unsigned int dppclk_mhz;
unsigned int phyclk_mhz;
#endif
}; };
/* This table is contiguous */ /* This table is contiguous */
...@@ -72,6 +97,26 @@ struct wm_range_table_entry { ...@@ -72,6 +97,26 @@ struct wm_range_table_entry {
bool valid; bool valid;
}; };
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
struct nv_wm_range_entry {
bool valid;
struct {
uint8_t wm_type;
uint16_t min_dcfclk;
uint16_t max_dcfclk;
uint16_t min_uclk;
uint16_t max_uclk;
} pmfw_breakdown;
struct {
double pstate_latency_us;
double sr_exit_time_us;
double sr_enter_plus_exit_time_us;
} dml_input;
};
#endif
struct clk_log_info { struct clk_log_info {
bool enabled; bool enabled;
...@@ -143,7 +188,14 @@ struct clk_bypass { ...@@ -143,7 +188,14 @@ struct clk_bypass {
* D occupied, C will be emptry. * D occupied, C will be emptry.
*/ */
struct wm_table { struct wm_table {
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
union {
struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
#endif
struct wm_range_table_entry entries[WM_SET_COUNT]; struct wm_range_table_entry entries[WM_SET_COUNT];
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
};
#endif
}; };
struct clk_bw_params { struct clk_bw_params {
...@@ -183,6 +235,20 @@ struct clk_mgr_funcs { ...@@ -183,6 +235,20 @@ struct clk_mgr_funcs {
bool (*are_clock_states_equal) (struct dc_clocks *a, bool (*are_clock_states_equal) (struct dc_clocks *a,
struct dc_clocks *b); struct dc_clocks *b);
void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
/*
* Send message to PMFW to set hard min memclk frequency
* When current_mode = false, set DPM0
* When current_mode = true, set required clock for current mode
*/
void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);
/* Send message to PMFW to set hard max memclk frequency to highest DPM */
void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);
/* Get current memclk states from PMFW, update relevant structures */
void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
#endif
}; };
struct clk_mgr { struct clk_mgr {
...@@ -190,6 +256,9 @@ struct clk_mgr { ...@@ -190,6 +256,9 @@ struct clk_mgr {
struct clk_mgr_funcs *funcs; struct clk_mgr_funcs *funcs;
struct dc_clocks clks; struct dc_clocks clks;
bool psr_allow_active_cache; bool psr_allow_active_cache;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
bool force_smu_not_present;
#endif
int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
int dentist_vco_freq_khz; int dentist_vco_freq_khz;
struct clk_state_registers_and_bypass boot_snapshot; struct clk_state_registers_and_bypass boot_snapshot;
......
...@@ -101,6 +101,12 @@ enum dentist_divider_range { ...@@ -101,6 +101,12 @@ enum dentist_divider_range {
CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
// TODO:
#define CLK_REG_LIST_DCN3() \
SR(DENTIST_DISPCLK_CNTL)
#endif
#define CLK_SF(reg_name, field_name, post_fix)\ #define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix .field_name = reg_name ## __ ## field_name ## post_fix
...@@ -167,6 +173,10 @@ struct clk_mgr_registers { ...@@ -167,6 +173,10 @@ struct clk_mgr_registers {
uint32_t CLK3_CLK2_DFS_CNTL; uint32_t CLK3_CLK2_DFS_CNTL;
uint32_t CLK3_CLK_PLL_REQ; uint32_t CLK3_CLK_PLL_REQ;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
uint32_t CLK0_CLK2_DFS_CNTL;
uint32_t CLK0_CLK_PLL_REQ;
#endif
uint32_t MP1_SMN_C2PMSG_67; uint32_t MP1_SMN_C2PMSG_67;
uint32_t MP1_SMN_C2PMSG_83; uint32_t MP1_SMN_C2PMSG_83;
uint32_t MP1_SMN_C2PMSG_91; uint32_t MP1_SMN_C2PMSG_91;
...@@ -260,6 +270,10 @@ struct clk_mgr_internal { ...@@ -260,6 +270,10 @@ struct clk_mgr_internal {
enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state max_clks_state;
enum dm_pp_clocks_state cur_min_clks_state; enum dm_pp_clocks_state cur_min_clks_state;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
bool smu_present;
#endif
}; };
struct clk_mgr_internal_funcs { struct clk_mgr_internal_funcs {
......
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