Commit 4e2056e0 authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats

6bpc is only legal for RGB and RAW pixel encodings. For the rest
the minimum is 8bpc. Set our lower limit accordingly.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190326142556.21176-6-ville.syrjala@linux.intel.comReviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
parent 632c7ad6
...@@ -1978,6 +1978,14 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, ...@@ -1978,6 +1978,14 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return 0; return 0;
} }
int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
{
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
return 6 * 3;
else
return 8 * 3;
}
static int static int
intel_dp_compute_link_config(struct intel_encoder *encoder, intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config, struct intel_crtc_state *pipe_config,
...@@ -2001,7 +2009,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, ...@@ -2001,7 +2009,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
limits.min_lane_count = 1; limits.min_lane_count = 1;
limits.max_lane_count = intel_dp_max_lane_count(intel_dp); limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
limits.min_bpp = 6 * 3; limits.min_bpp = intel_dp_min_bpp(pipe_config);
limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
if (intel_dp_is_edp(intel_dp)) { if (intel_dp_is_edp(intel_dp)) {
......
...@@ -34,6 +34,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, ...@@ -34,6 +34,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
struct link_config_limits *limits); struct link_config_limits *limits);
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state); const struct drm_connector_state *conn_state);
int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
i915_reg_t dp_reg, enum port port, i915_reg_t dp_reg, enum port port,
enum pipe *pipe); enum pipe *pipe);
......
...@@ -124,7 +124,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ...@@ -124,7 +124,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
limits.min_lane_count = limits.min_lane_count =
limits.max_lane_count = intel_dp_max_lane_count(intel_dp); limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
limits.min_bpp = 6 * 3; limits.min_bpp = intel_dp_min_bpp(pipe_config);
limits.max_bpp = pipe_config->pipe_bpp; limits.max_bpp = pipe_config->pipe_bpp;
intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
......
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