ISDN: More Eicon driver cosmetics

- moved some "//" remarks to "/* */"
- removed DOS carriage-return characters at end of line from one
  header-file.

(Armin Schindler)

drivers/isdn/hardware/eicon/s_4bri.c

@@ -249,12 +249,12 @@ static byte * qBri_check_FPGAsrc (PISDN_ADAPTER IoAdapter, char *FileName,
 
 /******************************************************************************/
 
-#define FPGA_PROG   0x0001		// PROG enable low
-#define FPGA_BUSY   0x0002		// BUSY high, DONE low
-#define	FPGA_CS     0x000C		// Enable I/O pins
+#define FPGA_PROG   0x0001		/* PROG enable low */
+#define FPGA_BUSY   0x0002		/* BUSY high, DONE low */
+#define	FPGA_CS     0x000C		/* Enable I/O pins */
 #define FPGA_CCLK   0x0100
 #define FPGA_DOUT   0x0400
-#define FPGA_DIN    FPGA_DOUT   // bidirectional I/O
+#define FPGA_DIN    FPGA_DOUT   /* bidirectional I/O */
 
 int qBri_FPGA_download (PISDN_ADAPTER IoAdapter) {
 	int            bit ;
@@ -296,9 +296,9 @@ int qBri_FPGA_download (PISDN_ADAPTER IoAdapter) {
 /*
  *	prepare download, pulse PROGRAM pin down.
  */
-	WRITE_WORD(addr, baseval & ~FPGA_PROG) ; // PROGRAM low pulse
-	WRITE_WORD(addr, baseval) ;              // release
-	diva_os_wait (50) ;  // wait until FPGA finished internal memory clear
+	WRITE_WORD(addr, baseval & ~FPGA_PROG) ; /* PROGRAM low pulse */
+	WRITE_WORD(addr, baseval) ;              /* release */
+	diva_os_wait (50) ;  /* wait until FPGA finished internal memory clear */
 /*
  *	check done pin, must be low
  */
@@ -315,14 +315,14 @@ int qBri_FPGA_download (PISDN_ADAPTER IoAdapter) {
 	{
 		val = ((word)File[code++]) << 3 ;
 
-		for ( bit = 8 ; bit-- > 0 ; val <<= 1 ) // put byte onto FPGA
+		for ( bit = 8 ; bit-- > 0 ; val <<= 1 ) /* put byte onto FPGA */
 		{
-			baseval &= ~FPGA_DOUT ;             // clr  data bit
-			baseval |= (val & FPGA_DOUT) ;      // copy data bit
+			baseval &= ~FPGA_DOUT ;             /* clr  data bit */
+			baseval |= (val & FPGA_DOUT) ;      /* copy data bit */
 			WRITE_WORD(addr, baseval) ;
-			WRITE_WORD(addr, baseval | FPGA_CCLK) ;     // set CCLK hi
-			WRITE_WORD(addr, baseval | FPGA_CCLK) ;     // set CCLK hi
-			WRITE_WORD(addr, baseval) ;                 // set CCLK lo
+			WRITE_WORD(addr, baseval | FPGA_CCLK) ;     /* set CCLK hi */
+			WRITE_WORD(addr, baseval | FPGA_CCLK) ;     /* set CCLK hi */
+			WRITE_WORD(addr, baseval) ;                 /* set CCLK lo */
 		}
 	}
 	xdiFreeFile (File) ;
@@ -868,7 +868,7 @@ static void disable_qBri_interrupt (PISDN_ADAPTER IoAdapter) {
 /*
  *	clear interrupt line (reset Local Interrupt Test Register)
  */
-	IoAdapter->reset[PLX9054_INTCSR] = 0x00 ;	// disable PCI interrupts
+	IoAdapter->reset[PLX9054_INTCSR] = 0x00 ;	/* disable PCI interrupts */
 	WRITE_DWORD(qBriIrq, MQ_IRQ_REQ_OFF) ;
 }
 

drivers/isdn/hardware/eicon/s_bri.c

@@ -459,9 +459,9 @@ static int bri_ISR (struct _ISDN_ADAPTER* IoAdapter) {
 static void disable_bri_interrupt (PISDN_ADAPTER IoAdapter) {
  if ( IoAdapter->reset )
  {
-  outpp (IoAdapter->reset, 0x00) ; // disable interrupts !
+  outpp (IoAdapter->reset, 0x00) ; /* disable interrupts ! */
  }
- outpp (IoAdapter->ctlReg, 0x00) ;    // clear int, halt cpu
+ outpp (IoAdapter->ctlReg, 0x00) ; /* clear int, halt cpu */
 }
 /* -------------------------------------------------------------------------
   Fill card entry points

drivers/isdn/hardware/eicon/s_pri.c

@@ -228,7 +228,7 @@ dsp_check_presence (volatile byte* addr, volatile byte* data, int dsp)
 static dword
 diva_pri_detect_dsps (PISDN_ADAPTER IoAdapter)
 {
-//  byte* base = a->resources.pci.addr[2];
+  /* byte* base = a->resources.pci.addr[2]; */
   byte* base = IoAdapter->reset - MP_RESET ;
   dword ret = 0, DspCount = 0 ;
   dword row_offset[] = {
@@ -242,12 +242,12 @@ diva_pri_detect_dsps (PISDN_ADAPTER IoAdapter)
   byte *dsp_addr_port, *dsp_data_port, row_state;
   int dsp_row = 0, dsp_index, dsp_num;
  IoAdapter->InitialDspInfo &= 0xffff ;
-//  if (!base || !a->xdi_adapter.reset)
+ /* if (!base || !a->xdi_adapter.reset) */
   if (!base || !IoAdapter->reset)
   {
     return (0);
   }
-//  *(volatile byte*)(a->xdi_adapter.reset) = _MP_RISC_RESET | _MP_DSP_RESET;
+  /* *(volatile byte*)(a->xdi_adapter.reset) = _MP_RISC_RESET | _MP_DSP_RESET; */
   *(volatile byte*)(IoAdapter->reset) = _MP_RISC_RESET | _MP_DSP_RESET;
   diva_os_wait (5) ;
   for (dsp_num = 0; dsp_num < 30; dsp_num++) {
@@ -264,7 +264,7 @@ diva_pri_detect_dsps (PISDN_ADAPTER IoAdapter)
    DspCount++ ;
     }
   }
-//  *(volatile byte*)(a->xdi_adapter.reset) = _MP_RISC_RESET | _MP_LED1 | _MP_LED2;
+  /* *(volatile byte*)(a->xdi_adapter.reset) = _MP_RISC_RESET | _MP_LED1 | _MP_LED2; */
   *(volatile byte*)(IoAdapter->reset) = _MP_RISC_RESET | _MP_LED1 | _MP_LED2;
   diva_os_wait (50) ;
   /*