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Commit 4f71fecd authored by Derek Robson's avatar Derek Robson Committed by Greg Kroah-Hartman
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staging: ccree: - style fix, spaces and tabs 

Changed code indent to be tabs across whole driver
Found using checkpatch
Signed-off-by: default avatarDerek Robson <robsonde@gmail.com>
Acked-by: default avatarGilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2bd25151
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Showing with 75 additions and 74 deletions
drivers/staging/ccree/ssi_cipher.c
View file @ 4f71fecd
...@@ -258,45 +258,45 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm) ...@@ -258,45 +258,45 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
typedef struct tdes_keys{ typedef struct tdes_keys{
u8 key1[DES_KEY_SIZE]; u8 key1[DES_KEY_SIZE];
u8 key2[DES_KEY_SIZE]; u8 key2[DES_KEY_SIZE];
u8 key3[DES_KEY_SIZE]; u8 key3[DES_KEY_SIZE];
}tdes_keys_t; }tdes_keys_t;
static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, static const u8 zero_buff[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
/* The function verifies that tdes keys are not weak.*/ /* The function verifies that tdes keys are not weak.*/
static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen) static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
{ {
#ifdef CCREE_FIPS_SUPPORT #ifdef CCREE_FIPS_SUPPORT
tdes_keys_t *tdes_key = (tdes_keys_t*)key; tdes_keys_t *tdes_key = (tdes_keys_t*)key;
/* verify key1 != key2 and key3 != key2*/ /* verify key1 != key2 and key3 != key2*/
if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, sizeof(tdes_key->key1)) == 0) || if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, sizeof(tdes_key->key1)) == 0) ||
(memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2, sizeof(tdes_key->key3)) == 0) )) { (memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2, sizeof(tdes_key->key3)) == 0) )) {
return -ENOEXEC; return -ENOEXEC;
} }
#endif /* CCREE_FIPS_SUPPORT */ #endif /* CCREE_FIPS_SUPPORT */
return 0; return 0;
} }
/* The function verifies that xts keys are not weak.*/ /* The function verifies that xts keys are not weak.*/
static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen) static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
{ {
#ifdef CCREE_FIPS_SUPPORT #ifdef CCREE_FIPS_SUPPORT
/* Weak key is define as key that its first half (128/256 lsb) equals its second half (128/256 msb) */ /* Weak key is define as key that its first half (128/256 lsb) equals its second half (128/256 msb) */
int singleKeySize = keylen >> 1; int singleKeySize = keylen >> 1;
if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) { if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) {
return -ENOEXEC; return -ENOEXEC;
} }
#endif /* CCREE_FIPS_SUPPORT */ #endif /* CCREE_FIPS_SUPPORT */
return 0; return 0;
} }
static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num) static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
...@@ -720,12 +720,13 @@ ssi_blkcipher_create_data_desc( ...@@ -720,12 +720,13 @@ ssi_blkcipher_create_data_desc(
} }
static int ssi_blkcipher_complete(struct device *dev, static int ssi_blkcipher_complete(struct device *dev,
struct ssi_ablkcipher_ctx *ctx_p, struct ssi_ablkcipher_ctx *ctx_p,
struct blkcipher_req_ctx *req_ctx, struct blkcipher_req_ctx *req_ctx,
struct scatterlist *dst, struct scatterlist *src, struct scatterlist *dst,
unsigned int ivsize, struct scatterlist *src,
void *areq, unsigned int ivsize,
void __iomem *cc_base) void *areq,
void __iomem *cc_base)
{ {
int completion_error = 0; int completion_error = 0;
u32 inflight_counter; u32 inflight_counter;
...@@ -779,7 +780,7 @@ static int ssi_blkcipher_process( ...@@ -779,7 +780,7 @@ static int ssi_blkcipher_process(
/* No data to process is valid */ /* No data to process is valid */
return 0; return 0;
} }
/*For CTS in case of data size aligned to 16 use CBC mode*/ /*For CTS in case of data size aligned to 16 use CBC mode*/
if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)){ if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)){
ctx_p->cipher_mode = DRV_CIPHER_CBC; ctx_p->cipher_mode = DRV_CIPHER_CBC;
......
drivers/staging/ccree/ssi_driver.c
View file @ 4f71fecd
...@@ -437,9 +437,9 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) ...@@ -437,9 +437,9 @@ static void cleanup_cc_resources(struct platform_device *plat_dev)
struct ssi_drvdata *drvdata = struct ssi_drvdata *drvdata =
(struct ssi_drvdata *)dev_get_drvdata(&plat_dev->dev); (struct ssi_drvdata *)dev_get_drvdata(&plat_dev->dev);
ssi_aead_free(drvdata); ssi_aead_free(drvdata);
ssi_hash_free(drvdata); ssi_hash_free(drvdata);
ssi_ablkcipher_free(drvdata); ssi_ablkcipher_free(drvdata);
ssi_ivgen_fini(drvdata); ssi_ivgen_fini(drvdata);
ssi_power_mgr_fini(drvdata); ssi_power_mgr_fini(drvdata);
ssi_buffer_mgr_fini(drvdata); ssi_buffer_mgr_fini(drvdata);
......
drivers/staging/ccree/ssi_driver.h
View file @ 4f71fecd
...@@ -110,9 +110,9 @@ struct ssi_crypto_req { ...@@ -110,9 +110,9 @@ struct ssi_crypto_req {
void *user_arg; void *user_arg;
dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES];
/* For the first 'ivgen_dma_addr_len' addresses of this array, /* For the first 'ivgen_dma_addr_len' addresses of this array,
* generated IV would be placed in it by send_request(). * generated IV would be placed in it by send_request().
* Same generated IV for all addresses! * Same generated IV for all addresses!
*/ */
unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */ unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */
unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */ unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */
struct completion seq_compl; /* request completion */ struct completion seq_compl; /* request completion */
......
drivers/staging/ccree/ssi_fips.h
View file @ 4f71fecd
...@@ -23,10 +23,10 @@ ...@@ -23,10 +23,10 @@
*/ */
typedef enum ssi_fips_state { typedef enum ssi_fips_state {
CC_FIPS_STATE_NOT_SUPPORTED = 0, CC_FIPS_STATE_NOT_SUPPORTED = 0,
CC_FIPS_STATE_SUPPORTED, CC_FIPS_STATE_SUPPORTED,
CC_FIPS_STATE_ERROR, CC_FIPS_STATE_ERROR,
CC_FIPS_STATE_RESERVE32B = S32_MAX CC_FIPS_STATE_RESERVE32B = S32_MAX
} ssi_fips_state_t; } ssi_fips_state_t;
......
drivers/staging/ccree/ssi_fips_ext.c
View file @ 4f71fecd
...@@ -39,7 +39,7 @@ static ssi_fips_error_t fips_error = CC_REE_FIPS_ERROR_OK; ...@@ -39,7 +39,7 @@ static ssi_fips_error_t fips_error = CC_REE_FIPS_ERROR_OK;
*/ */
int ssi_fips_ext_get_state(ssi_fips_state_t *p_state) int ssi_fips_ext_get_state(ssi_fips_state_t *p_state)
{ {
int rc = 0; int rc = 0;
if (p_state == NULL) { if (p_state == NULL) {
return -EINVAL; return -EINVAL;
...@@ -58,7 +58,7 @@ int ssi_fips_ext_get_state(ssi_fips_state_t *p_state) ...@@ -58,7 +58,7 @@ int ssi_fips_ext_get_state(ssi_fips_state_t *p_state)
*/ */
int ssi_fips_ext_get_error(ssi_fips_error_t *p_err) int ssi_fips_ext_get_error(ssi_fips_error_t *p_err)
{ {
int rc = 0; int rc = 0;
if (p_err == NULL) { if (p_err == NULL) {
return -EINVAL; return -EINVAL;
......
drivers/staging/ccree/ssi_fips_ll.c
View file @ 4f71fecd
...@@ -233,8 +233,8 @@ static const FipsCmacData FipsCmacDataTable[] = { ...@@ -233,8 +233,8 @@ static const FipsCmacData FipsCmacDataTable[] = {
#define FIPS_CMAC_NUM_OF_TESTS (sizeof(FipsCmacDataTable) / sizeof(FipsCmacData)) #define FIPS_CMAC_NUM_OF_TESTS (sizeof(FipsCmacDataTable) / sizeof(FipsCmacData))
static const FipsHashData FipsHashDataTable[] = { static const FipsHashData FipsHashDataTable[] = {
{ DRV_HASH_SHA1, NIST_SHA_1_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_1_MD }, { DRV_HASH_SHA1, NIST_SHA_1_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_1_MD },
{ DRV_HASH_SHA256, NIST_SHA_256_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_256_MD }, { DRV_HASH_SHA256, NIST_SHA_256_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_256_MD },
#if (CC_SUPPORT_SHA > 256) #if (CC_SUPPORT_SHA > 256)
// { DRV_HASH_SHA512, NIST_SHA_512_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_512_MD }, // { DRV_HASH_SHA512, NIST_SHA_512_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_512_MD },
#endif #endif
...@@ -242,8 +242,8 @@ static const FipsHashData FipsHashDataTable[] = { ...@@ -242,8 +242,8 @@ static const FipsHashData FipsHashDataTable[] = {
#define FIPS_HASH_NUM_OF_TESTS (sizeof(FipsHashDataTable) / sizeof(FipsHashData)) #define FIPS_HASH_NUM_OF_TESTS (sizeof(FipsHashDataTable) / sizeof(FipsHashData))
static const FipsHmacData FipsHmacDataTable[] = { static const FipsHmacData FipsHmacDataTable[] = {
{ DRV_HASH_SHA1, NIST_HMAC_SHA1_KEY, NIST_HMAC_SHA1_KEY_SIZE, NIST_HMAC_SHA1_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA1_MD }, { DRV_HASH_SHA1, NIST_HMAC_SHA1_KEY, NIST_HMAC_SHA1_KEY_SIZE, NIST_HMAC_SHA1_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA1_MD },
{ DRV_HASH_SHA256, NIST_HMAC_SHA256_KEY, NIST_HMAC_SHA256_KEY_SIZE, NIST_HMAC_SHA256_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA256_MD }, { DRV_HASH_SHA256, NIST_HMAC_SHA256_KEY, NIST_HMAC_SHA256_KEY_SIZE, NIST_HMAC_SHA256_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA256_MD },
#if (CC_SUPPORT_SHA > 256) #if (CC_SUPPORT_SHA > 256)
// { DRV_HASH_SHA512, NIST_HMAC_SHA512_KEY, NIST_HMAC_SHA512_KEY_SIZE, NIST_HMAC_SHA512_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA512_MD }, // { DRV_HASH_SHA512, NIST_HMAC_SHA512_KEY, NIST_HMAC_SHA512_KEY_SIZE, NIST_HMAC_SHA512_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA512_MD },
#endif #endif
...@@ -251,22 +251,22 @@ static const FipsHmacData FipsHmacDataTable[] = { ...@@ -251,22 +251,22 @@ static const FipsHmacData FipsHmacDataTable[] = {
#define FIPS_HMAC_NUM_OF_TESTS (sizeof(FipsHmacDataTable) / sizeof(FipsHmacData)) #define FIPS_HMAC_NUM_OF_TESTS (sizeof(FipsHmacDataTable) / sizeof(FipsHmacData))
static const FipsCcmData FipsCcmDataTable[] = { static const FipsCcmData FipsCcmDataTable[] = {
{ DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC }, { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC },
{ DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC }, { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC },
{ DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC }, { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC },
{ DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC }, { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC },
{ DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC }, { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC },
{ DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC }, { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC },
}; };
#define FIPS_CCM_NUM_OF_TESTS (sizeof(FipsCcmDataTable) / sizeof(FipsCcmData)) #define FIPS_CCM_NUM_OF_TESTS (sizeof(FipsCcmDataTable) / sizeof(FipsCcmData))
static const FipsGcmData FipsGcmDataTable[] = { static const FipsGcmData FipsGcmDataTable[] = {
{ DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC }, { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC },
{ DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC }, { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC },
{ DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC }, { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC },
{ DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC }, { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC },
{ DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC }, { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC },
{ DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC }, { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC },
}; };
#define FIPS_GCM_NUM_OF_TESTS (sizeof(FipsGcmDataTable) / sizeof(FipsGcmData)) #define FIPS_GCM_NUM_OF_TESTS (sizeof(FipsGcmDataTable) / sizeof(FipsGcmData))
...@@ -758,7 +758,7 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, ...@@ -758,7 +758,7 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer,
FIPS_LOG("ssi_hash_fips_run_test %d returned error - rc = %d \n", i, rc); FIPS_LOG("ssi_hash_fips_run_test %d returned error - rc = %d \n", i, rc);
error = FIPS_HashToFipsError(hash_data->hash_mode); error = FIPS_HashToFipsError(hash_data->hash_mode);
break; break;
} }
/* compare actual mac result to expected */ /* compare actual mac result to expected */
if (memcmp(virt_ctx->mac_res, hash_data->mac_res, digest_size) != 0) if (memcmp(virt_ctx->mac_res, hash_data->mac_res, digest_size) != 0)
...@@ -773,7 +773,7 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, ...@@ -773,7 +773,7 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer,
error = FIPS_HashToFipsError(hash_data->hash_mode); error = FIPS_HashToFipsError(hash_data->hash_mode);
break; break;
} }
} }
return error; return error;
...@@ -1317,9 +1317,9 @@ ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, ...@@ -1317,9 +1317,9 @@ ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer,
if (memcmp(virt_ctx->dout, ccmData->dataOut, ccmData->dataInSize) != 0) if (memcmp(virt_ctx->dout, ccmData->dataOut, ccmData->dataInSize) != 0)
{ {
FIPS_LOG("dout comparison error %d - size=%d \n", i, ccmData->dataInSize); FIPS_LOG("dout comparison error %d - size=%d \n", i, ccmData->dataInSize);
error = CC_REE_FIPS_ERROR_AESCCM_PUT; error = CC_REE_FIPS_ERROR_AESCCM_PUT;
break; break;
} }
/* compare actual mac result to expected */ /* compare actual mac result to expected */
if (memcmp(virt_ctx->mac_res, ccmData->macResOut, ccmData->tagSize) != 0) if (memcmp(virt_ctx->mac_res, ccmData->macResOut, ccmData->tagSize) != 0)
......
drivers/staging/ccree/ssi_fips_local.c
View file @ 4f71fecd
...@@ -264,32 +264,32 @@ int ssi_fips_set_state(ssi_fips_state_t state) ...@@ -264,32 +264,32 @@ int ssi_fips_set_state(ssi_fips_state_t state)
int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, ssi_fips_error_t err) int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, ssi_fips_error_t err)
{ {
int rc = 0; int rc = 0;
ssi_fips_error_t current_err; ssi_fips_error_t current_err;
FIPS_LOG("ssi_fips_set_error - fips_error = %d \n", err); FIPS_LOG("ssi_fips_set_error - fips_error = %d \n", err);
// setting no error is not allowed // setting no error is not allowed
if (err == CC_REE_FIPS_ERROR_OK) { if (err == CC_REE_FIPS_ERROR_OK) {
return -ENOEXEC; return -ENOEXEC;
}
// If error exists, do not set new error
if (ssi_fips_get_error(&current_err) != 0) {
return -ENOEXEC;
} }
// If error exists, do not set new error if (current_err != CC_REE_FIPS_ERROR_OK) {
if (ssi_fips_get_error(&current_err) != 0) { return -ENOEXEC;
return -ENOEXEC; }
} // set REE internal error and state
if (current_err != CC_REE_FIPS_ERROR_OK) {
return -ENOEXEC;
}
// set REE internal error and state
rc = ssi_fips_ext_set_error(err); rc = ssi_fips_ext_set_error(err);
if (rc != 0) { if (rc != 0) {
return -ENOEXEC; return -ENOEXEC;
} }
rc = ssi_fips_ext_set_state(CC_FIPS_STATE_ERROR); rc = ssi_fips_ext_set_state(CC_FIPS_STATE_ERROR);
if (rc != 0) { if (rc != 0) {
return -ENOEXEC; return -ENOEXEC;
} }
// push error towards TEE libraray, if it's not TEE error // push error towards TEE libraray, if it's not TEE error
if (err != CC_REE_FIPS_ERROR_FROM_TEE) { if (err != CC_REE_FIPS_ERROR_FROM_TEE) {
ssi_fips_update_tee_upon_ree_status(p_drvdata, err); ssi_fips_update_tee_upon_ree_status(p_drvdata, err);
} }
......
drivers/staging/ccree/ssi_fips_local.h
View file @ 4f71fecd
...@@ -34,14 +34,14 @@ typedef enum CC_FipsSyncStatus{ ...@@ -34,14 +34,14 @@ typedef enum CC_FipsSyncStatus{
#define CHECK_AND_RETURN_UPON_FIPS_ERROR() {\ #define CHECK_AND_RETURN_UPON_FIPS_ERROR() {\
if (ssi_fips_check_fips_error() != 0) {\ if (ssi_fips_check_fips_error() != 0) {\
return -ENOEXEC;\ return -ENOEXEC;\
}\ }\
} }
#define CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR() {\ #define CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR() {\
if (ssi_fips_check_fips_error() != 0) {\ if (ssi_fips_check_fips_error() != 0) {\
return;\ return;\
}\ }\
} }
#define SSI_FIPS_INIT(p_drvData) (ssi_fips_init(p_drvData)) #define SSI_FIPS_INIT(p_drvData) (ssi_fips_init(p_drvData))
#define SSI_FIPS_FINI(p_drvData) (ssi_fips_fini(p_drvData)) #define SSI_FIPS_FINI(p_drvData) (ssi_fips_fini(p_drvData))
......
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