Commit 5143c953 authored by Benoît Thébaudeau's avatar Benoît Thébaudeau Committed by Ulf Hansson

mmc: sdhci-esdhc-imx: Allow all supported prescaler values

On i.MX, SYSCTL.SDCLKFS may always be set to 0 in order to make the SD
clock frequency prescaler divide by 1 in SDR mode, even with the eSDHC.
The previous minimum prescaler value of 2 in SDR mode with the eSDHC was
a code remnant from PowerPC, which actually has this limitation on
earlier revisions.

In DDR mode, the prescaler can divide by up to 512.

The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
this change makes it possible to get 48 MHz from the USB PLL
(240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
(240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
Signed-off-by: default avatarBenoît Thébaudeau <benoit@wsystem.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 81a0a8bc
...@@ -674,7 +674,8 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, ...@@ -674,7 +674,8 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
unsigned int host_clock = pltfm_host->clock; unsigned int host_clock = pltfm_host->clock;
int pre_div = 2; int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
int pre_div = 1;
int div = 1; int div = 1;
u32 temp, val; u32 temp, val;
...@@ -689,28 +690,23 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, ...@@ -689,28 +690,23 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
return; return;
} }
if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
pre_div = 1;
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
| ESDHC_CLOCK_MASK); | ESDHC_CLOCK_MASK);
sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
while (host_clock / pre_div / 16 > clock && pre_div < 256) while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
pre_div < 256)
pre_div *= 2; pre_div *= 2;
while (host_clock / pre_div / div > clock && div < 16) while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
div++; div++;
host->mmc->actual_clock = host_clock / pre_div / div; host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
clock, host->mmc->actual_clock); clock, host->mmc->actual_clock);
if (imx_data->is_ddr) pre_div >>= 1;
pre_div >>= 2;
else
pre_div >>= 1;
div--; div--;
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
......
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