Commit 5190c08b authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner

clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 9c4d6e55
...@@ -10,6 +10,7 @@ obj-y += clk-inverter.o ...@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
obj-y += clk-mmc-phase.o obj-y += clk-mmc-phase.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-y += clk-rk3036.o
obj-y += clk-rk3188.o obj-y += clk-rk3188.o
obj-y += clk-rk3288.o obj-y += clk-rk3288.o
obj-y += clk-rk3368.o obj-y += clk-rk3368.o
This diff is collapsed.
...@@ -33,7 +33,7 @@ struct clk; ...@@ -33,7 +33,7 @@ struct clk;
#define HIWORD_UPDATE(val, mask, shift) \ #define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16)) ((val) << (shift) | (mask) << ((shift) + 16))
/* register positions shared by RK2928, RK3066 and RK3188 */ /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
#define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40 #define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
...@@ -43,6 +43,13 @@ struct clk; ...@@ -43,6 +43,13 @@ struct clk;
#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
#define RK2928_MISC_CON 0x134 #define RK2928_MISC_CON 0x134
#define RK3036_SDMMC_CON0 0x144
#define RK3036_SDMMC_CON1 0x148
#define RK3036_SDIO_CON0 0x14c
#define RK3036_SDIO_CON1 0x150
#define RK3036_EMMC_CON0 0x154
#define RK3036_EMMC_CON1 0x158
#define RK3288_PLL_CON(x) RK2928_PLL_CON(x) #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3288_MODE_CON 0x50 #define RK3288_MODE_CON 0x50
#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
......
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