Commit 541d7c44 authored by Thierry Reding's avatar Thierry Reding

arm64: tegra: Sort device tree nodes alphabetically

Device tree nodes without unit-address are to be sorted alphabetically.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 434e8aed
...@@ -1127,6 +1127,30 @@ cpu_bpmp_rx: shmem@4f000 { ...@@ -1127,6 +1127,30 @@ cpu_bpmp_rx: shmem@4f000 {
}; };
}; };
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
nvidia,bpmp-bus-id = <5>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
bpmp_thermal: thermal {
compatible = "nvidia,tegra186-bpmp-thermal";
#thermal-sensor-cells = <1>;
};
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -1228,30 +1252,6 @@ L2_A57: l2-cache1 { ...@@ -1228,30 +1252,6 @@ L2_A57: l2-cache1 {
}; };
}; };
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
nvidia,bpmp-bus-id = <5>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
bpmp_thermal: thermal {
compatible = "nvidia,tegra186-bpmp-thermal";
#thermal-sensor-cells = <1>;
};
};
thermal-zones { thermal-zones {
a57 { a57 {
polling-delay = <0>; polling-delay = <0>;
......
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