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Commit 54c3cf65 authored by Kevin Hilman's avatar Kevin Hilman
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Merge tag 'omap-for-v4.3/fixes-rc1' of... 

Merge tag 'omap-for-v4.3/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Merge "omap fixes against v4.3-rc1" from Tony Lindgren:

Fixes for omaps against v4.3-rc1:

- Fix long time regression on beagle for tfp410 pin muxing

- Fix dm814x control base address typo and related Ethernet
  phy configuration

- Fix igepv2 Ethernet pinmuxing as only some boards have it

- Fix pbias regulator compatible values as a pending regulator
  fix needs those for MMC1 to work properly

- Fix beagle-x15 MMC1 regulator and make pcf857x built-in

- Fix omap5 and dra7 Kconfig options when built as the only
  SoCs selected

- Fix PM errata for omap5 and dra7 as they too need it

- Fix phycore mpu voltage

Also included are a few cosmetic fixes:

- Remove unused of_irq macros

- Fix dra7 ethernet name

* tag 'omap-for-v4.3/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Fixup model name for HP t410 dts
  ARM: dts: DRA7: fix a typo in ethernet
  ARM: omap2plus_defconfig: make PCF857x built-in
  ARM: dts: Use ti,pbias compatible string for pbias
  ARM: OMAP5: Cleanup options for SoC only build
  ARM: DRA7: Select missing options for SoC only build
  ARM: OMAP2+: board-generic: Remove stale of_irq macros
  ARM: OMAP4+: PM: erratum is used by OMAP5 and DRA7 as well
  ARM: dts: omap3-igep: Move eth IRQ pinmux to IGEPv2 common dtsi
  ARM: dts: am57xx-beagle-x15: Add wakeup irq for mcp79410
  ARM: dts: am335x-phycore-som: Fix mpu voltage
  ARM: dts: am57xx-beagle-x15: Fix regulator populated in MMC1 dt node
  ARM: dts: Fix dm814x control base to properly initialize Ethernet PHY
  ARM: dts: omap3-beagle: make i2c3, ddc and tfp410 gpio work again
parents 6ff33f39 60fdcb88
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Showing with 34 additions and 36 deletions
arch/arm/boot/dts/am335x-phycore-som.dtsi
View file @ 54c3cf65
......@@ -252,10 +252,10 @@ vio_reg: regulator@1 {
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};
......
arch/arm/boot/dts/am57xx-beagle-x15.dts
View file @ 54c3cf65
......@@ -517,7 +517,8 @@ &i2c3 {
mcp_rtc: rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
<&dra7_pmx_core 0x424>;
pinctrl-names = "default";
pinctrl-0 = <&mcp79410_pins_default>;
......@@ -579,7 +580,6 @@ &mmc1 {
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
vmmc_aux-supply = <&vdd_3v3>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
......
arch/arm/boot/dts/dm8148-evm.dts
View file @ 54c3cf65
......@@ -19,10 +19,10 @@ memory {
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
phy-mode = "rgmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
phy-mode = "rgmii";
};
arch/arm/boot/dts/dm8148-t410.dts
View file @ 54c3cf65
......@@ -8,7 +8,7 @@
#include "dm814x.dtsi"
/ {
model = "DM8148 EVM";
model = "HP t410 Smart Zero Client";
compatible = "hp,t410", "ti,dm8148";
memory {
......@@ -19,10 +19,10 @@ memory {
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
phy-mode = "rgmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
phy-mode = "rgmii";
};
arch/arm/boot/dts/dm814x.dtsi
View file @ 54c3cf65
......@@ -181,9 +181,9 @@ timer3: timer@42000 {
ti,hwmods = "timer3";
};
control: control@160000 {
control: control@140000 {
compatible = "ti,dm814-scm", "simple-bus";
reg = <0x160000 0x16d000>;
reg = <0x140000 0x16d000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x160000 0x16d000>;
......@@ -321,9 +321,9 @@ cpsw_emac1: slave@4a100300 {
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@0x48160650 {
phy_sel: cpsw-phy-sel@48140650 {
compatible = "ti,am3352-cpsw-phy-sel";
reg= <0x48160650 0x4>;
reg= <0x48140650 0x4>;
reg-names = "gmii-sel";
};
};
......
arch/arm/boot/dts/dra7.dtsi
View file @ 54c3cf65
......@@ -122,7 +122,7 @@ scm_conf: scm_conf@0 {
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-dra7", "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
......@@ -1417,7 +1417,7 @@ crossbar_mpu: crossbar@4a002a48 {
ti,irqs-safe-map = <0>;
};
mac: ethernet@4a100000 {
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
......
arch/arm/boot/dts/omap2430.dtsi
View file @ 54c3cf65
......@@ -63,7 +63,7 @@ scm_clocks: clocks {
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-omap2", "ti,pbias-omap";
reg = <0x230 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
......
arch/arm/boot/dts/omap3-beagle.dts
View file @ 54c3cf65
......@@ -202,7 +202,7 @@ uart3_pins: pinmux_uart3_pins {
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
0x194 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
......
arch/arm/boot/dts/omap3-igep.dtsi
View file @ 54c3cf65
......@@ -78,12 +78,6 @@ mmc2_pins: pinmux_mmc2_pins {
>;
};
smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = <
0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
......
arch/arm/boot/dts/omap3-igep0020-common.dtsi
View file @ 54c3cf65
......@@ -156,6 +156,12 @@ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
>;
};
smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>;
};
};
&omap3_pmx_core2 {
......
arch/arm/boot/dts/omap3.dtsi
View file @ 54c3cf65
......@@ -203,7 +203,7 @@ sdma: dma-controller@48056000 {
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-omap3", "ti,pbias-omap";
reg = <0x2b0 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
......
arch/arm/boot/dts/omap4.dtsi
View file @ 54c3cf65
......@@ -198,7 +198,7 @@ omap4_padconf_global: omap4_padconf_global@5a0 {
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-omap4", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap4 {
......
arch/arm/boot/dts/omap5.dtsi
View file @ 54c3cf65
......@@ -187,7 +187,7 @@ omap5_padconf_global: omap5_padconf_global@5a0 {
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-omap5", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap5 {
......
arch/arm/configs/omap2plus_defconfig
View file @ 54c3cf65
......@@ -240,7 +240,7 @@ CONFIG_SSI_PROTOCOL=m
CONFIG_PINCTRL_SINGLE=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_PALMAS=y
CONFIG_W1=m
......
arch/arm/mach-omap2/Kconfig
View file @ 54c3cf65
......@@ -44,10 +44,11 @@ config SOC_OMAP5
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_ARM_ARCH_TIMER
select ARM_ERRATA_798181 if SMP
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP if PM
config SOC_AM33XX
bool "TI AM33XX"
......@@ -70,10 +71,13 @@ config SOC_DRA7XX
select ARCH_OMAP2PLUS
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_ARCH_TIMER
select IRQ_CROSSBAR
select ARM_ERRATA_798181 if SMP
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP if PM
config ARCH_OMAP2PLUS
bool
......
arch/arm/mach-omap2/board-generic.c
View file @ 54c3cf65
......@@ -20,13 +20,6 @@
#include "common.h"
#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
#define intc_of_init NULL
#endif
#ifndef CONFIG_ARCH_OMAP4
#define gic_of_init NULL
#endif
static const struct of_device_id omap_dt_match_table[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "ti,omap-infra", },
......
arch/arm/mach-omap2/pm.h
View file @ 54c3cf65
......@@ -103,7 +103,8 @@ static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
#define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1)
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) ||\
defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
extern u16 pm44xx_errata;
#define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id))
#else
......
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