[PATCH] Update IOP3xx I2C bus driver

The following patch is a major cleanup of the IOP3xx I2C bus driver
that is found on Intel's IOP and IXP chipsets. The existing driver in
the 2.6 tree uses hardcoded I/O addresses based on board configuration
which is just going to get ugly as more chips use this unit. The update
switches to using the driver model and passing in the I/O addresses
via platform_device resources. The patch also updates the ID name to
more closely match the actual usage of the device.

I have tested this new driver on IXP46x systems and Dave Jiang has
tested it on both IOP321 and IOP331 systems. ARM-specific patches
to provide platform-level hooks will go upstream after this patch
is integrated.

An example of using the new driver (from IXP46x ARM code) follows:

static struct resource ixp46x_i2c_resources[] = {
	[0] = {
		.start 	= 0xc8011000,
		.end	= 0xc801101c,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start 	= IRQ_IXP4XX_I2C,
		.end	= IRQ_IXP4XX_I2C,
		.flags	= IORESOURCE_IRQ
	}
};

static struct platform_device ixp46x_i2c_controller = {
	.name		= "IOP3xx-I2C",
	.id		= 0,
	.num_resources	= 2,
	.resource	= &ixp46x_i2c_resources
};

static struct platform_device *ixp46x_devices[] __initdata = {
	&ixp46x_i2c_controller
};

void __init ixp4xx_init(void)
{
	if (cpu_is_ixp46x()) {
		platform_add_devices(ixp46x_devices,
				ARRAY_SIZE(ixp46x_devices));
	}
}
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Greg Kroah-Hartman <greg@kroah.com>

drivers/i2c/busses/Kconfig

@@ -143,8 +143,14 @@ config I2C_IBM_IIC
 	  will be called i2c-ibm_iic.
 
 config I2C_IOP3XX
-	tristate "Intel XScale IOP3xx on-chip I2C interface"
-	depends on ARCH_IOP3XX && I2C
+	tristate "Intel IOP3xx and IXP4xx on-chip I2C interface"
+	depends on (ARCH_IOP3XX || ARCH_IXP4XX) && I2C
+	help
+	  Say Y here if you want to use the IIC bus controller on
+	  the Intel IOP3xx I/O Processors or IXP4xx Network Processors.
+
+	  This driver can also be built as a module.  If so, the module
+	  will be called i2c-iop3xx.
 
 config I2C_ISA
 	tristate "ISA Bus support"

drivers/i2c/busses/i2c-iop3xx.h

@@ -25,20 +25,20 @@
 /*
  * iop321 hardware bit definitions
  */
-#define IOP321_ICR_FAST_MODE	0x8000	/* 1=400kBps, 0=100kBps */
-#define IOP321_ICR_UNIT_RESET	0x4000	/* 1=RESET */
-#define IOP321_ICR_SADIE	0x2000	/* 1=Slave Detect Interrupt Enable */
-#define IOP321_ICR_ALDIE	0x1000	/* 1=Arb Loss Detect Interrupt Enable */
-#define IOP321_ICR_SSDIE	0x0800	/* 1=Slave STOP Detect Interrupt Enable */
-#define IOP321_ICR_BERRIE	0x0400	/* 1=Bus Error Interrupt Enable */
-#define IOP321_ICR_RXFULLIE	0x0200	/* 1=Receive Full Interrupt Enable */
-#define IOP321_ICR_TXEMPTYIE	0x0100	/* 1=Transmit Empty Interrupt Enable */
-#define IOP321_ICR_GCD		0x0080	/* 1=General Call Disable */
+#define IOP3XX_ICR_FAST_MODE	0x8000	/* 1=400kBps, 0=100kBps */
+#define IOP3XX_ICR_UNIT_RESET	0x4000	/* 1=RESET */
+#define IOP3XX_ICR_SAD_IE	0x2000	/* 1=Slave Detect Interrupt Enable */
+#define IOP3XX_ICR_ALD_IE	0x1000	/* 1=Arb Loss Detect Interrupt Enable */
+#define IOP3XX_ICR_SSD_IE	0x0800	/* 1=Slave STOP Detect Interrupt Enable */
+#define IOP3XX_ICR_BERR_IE	0x0400	/* 1=Bus Error Interrupt Enable */
+#define IOP3XX_ICR_RXFULL_IE	0x0200	/* 1=Receive Full Interrupt Enable */
+#define IOP3XX_ICR_TXEMPTY_IE	0x0100	/* 1=Transmit Empty Interrupt Enable */
+#define IOP3XX_ICR_GCD		0x0080	/* 1=General Call Disable */
 /*
- * IOP321_ICR_GCD: 1 disables response as slave. "This bit must be set
+ * IOP3XX_ICR_GCD: 1 disables response as slave. "This bit must be set
  * when sending a master mode general call message from the I2C unit"
  */
-#define IOP321_ICR_UE		0x0040	/* 1=Unit Enable */
+#define IOP3XX_ICR_UE		0x0040	/* 1=Unit Enable */
 /*
  * "NOTE: To avoid I2C bus integrity problems, 
  * the user needs to ensure that the GPIO Output Data Register - 
@@ -47,38 +47,38 @@
  * The user prepares to enable I2C port 0 and 
  * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
  */
-#define IOP321_ICR_SCLEN	0x0020	/* 1=SCL enable for master mode */
-#define IOP321_ICR_MABORT	0x0010	/* 1=Send a STOP with no data 
+#define IOP3XX_ICR_SCLEN	0x0020	/* 1=SCL enable for master mode */
+#define IOP3XX_ICR_MABORT	0x0010	/* 1=Send a STOP with no data 
 					 * NB TBYTE must be clear */
-#define IOP321_ICR_TBYTE	0x0008	/* 1=Send/Receive a byte. i2c clears */
-#define IOP321_ICR_NACK		0x0004	/* 1=reply with NACK */
-#define IOP321_ICR_MSTOP	0x0002	/* 1=send a STOP after next data byte */
-#define IOP321_ICR_MSTART	0x0001	/* 1=initiate a START */
+#define IOP3XX_ICR_TBYTE	0x0008	/* 1=Send/Receive a byte. i2c clears */
+#define IOP3XX_ICR_NACK		0x0004	/* 1=reply with NACK */
+#define IOP3XX_ICR_MSTOP	0x0002	/* 1=send a STOP after next data byte */
+#define IOP3XX_ICR_MSTART	0x0001	/* 1=initiate a START */
 
 
-#define IOP321_ISR_BERRD	0x0400	/* 1=BUS ERROR Detected */
-#define IOP321_ISR_SAD		0x0200	/* 1=Slave ADdress Detected */
-#define IOP321_ISR_GCAD		0x0100	/* 1=General Call Address Detected */
-#define IOP321_ISR_RXFULL	0x0080	/* 1=Receive Full */
-#define IOP321_ISR_TXEMPTY	0x0040	/* 1=Transmit Empty */
-#define IOP321_ISR_ALD		0x0020	/* 1=Arbitration Loss Detected */
-#define IOP321_ISR_SSD		0x0010	/* 1=Slave STOP Detected */
-#define IOP321_ISR_BBUSY	0x0008	/* 1=Bus BUSY */
-#define IOP321_ISR_UNITBUSY	0x0004	/* 1=Unit Busy */
-#define IOP321_ISR_NACK		0x0002	/* 1=Unit Rx or Tx a NACK */
-#define IOP321_ISR_RXREAD	0x0001	/* 1=READ 0=WRITE (R/W bit of slave addr */
+#define IOP3XX_ISR_BERRD	0x0400	/* 1=BUS ERROR Detected */
+#define IOP3XX_ISR_SAD		0x0200	/* 1=Slave ADdress Detected */
+#define IOP3XX_ISR_GCAD		0x0100	/* 1=General Call Address Detected */
+#define IOP3XX_ISR_RXFULL	0x0080	/* 1=Receive Full */
+#define IOP3XX_ISR_TXEMPTY	0x0040	/* 1=Transmit Empty */
+#define IOP3XX_ISR_ALD		0x0020	/* 1=Arbitration Loss Detected */
+#define IOP3XX_ISR_SSD		0x0010	/* 1=Slave STOP Detected */
+#define IOP3XX_ISR_BBUSY	0x0008	/* 1=Bus BUSY */
+#define IOP3XX_ISR_UNITBUSY	0x0004	/* 1=Unit Busy */
+#define IOP3XX_ISR_NACK		0x0002	/* 1=Unit Rx or Tx a NACK */
+#define IOP3XX_ISR_RXREAD	0x0001	/* 1=READ 0=WRITE (R/W bit of slave addr */
 
-#define IOP321_ISR_CLEARBITS	0x07f0
+#define IOP3XX_ISR_CLEARBITS	0x07f0
 
-#define IOP321_ISAR_SAMASK	0x007f
+#define IOP3XX_ISAR_SAMASK	0x007f
 
-#define IOP321_IDBR_MASK	0x00ff
+#define IOP3XX_IDBR_MASK	0x00ff
 
-#define IOP321_IBMR_SCL		0x0002
-#define IOP321_IBMR_SDA		0x0001
+#define IOP3XX_IBMR_SCL		0x0002
+#define IOP3XX_IBMR_SDA		0x0001
 
-#define IOP321_GPOD_I2C0	0x00c0	/* clear these bits to enable ch0 */
-#define IOP321_GPOD_I2C1	0x0030	/* clear these bits to enable ch1 */
+#define IOP3XX_GPOD_I2C0	0x00c0	/* clear these bits to enable ch0 */
+#define IOP3XX_GPOD_I2C1	0x0030	/* clear these bits to enable ch1 */
 
 #define MYSAR			0x02	/* SWAG a suitable slave address */
 
@@ -87,32 +87,21 @@
 #define I2C_ERR_ALD		(I2C_ERR+1)
 
 
-struct iop3xx_biu {                /* Bus Interface Unit - the hardware */
-/* physical hardware defs - regs*/
-	u32 *CR;
-	u32 *SR;
-	u32 *SAR;
-	u32 *DBR;
-	u32 *BMR;
-/* irq bit vector */
-	u32 irq;
-/* stored flags */
-	u32 SR_enabled, SR_received;
-};
+#define	CR_OFFSET		0
+#define	SR_OFFSET		0x4
+#define	SAR_OFFSET		0x8
+#define	DBR_OFFSET		0xc
+#define	CCR_OFFSET		0x10
+#define	BMR_OFFSET		0x14
 
-struct i2c_algo_iop3xx_data {
-	int channel;
+#define	IOP3XX_I2C_IO_SIZE	0x18
 
+struct i2c_algo_iop3xx_data {
+	u32 ioaddr;
 	wait_queue_head_t waitq;
 	spinlock_t lock;
-	int timeout;
-	struct iop3xx_biu* biu;
+	u32 SR_enabled, SR_received;
+	int id;
 };
 
-#define REGION_START(adap)	((u32)((adap)->biu->CR))
-#define REGION_END(adap)	((u32)((adap)->biu->BMR+1))
-#define REGION_LENGTH(adap)	(REGION_END(adap)-REGION_START(adap))
-
-#define IRQ_STATUS_MASK(adap)	(1<<adap->biu->irq)
-
 #endif /* I2C_IOP3XX_H */

include/linux/i2c-id.h

@@ -194,7 +194,7 @@
 #define I2C_ALGO_MPC8XX 0x110000	/* MPC8xx PowerPC I2C algorithm */
 #define I2C_ALGO_OCP    0x120000	/* IBM or otherwise On-chip I2C algorithm */
 #define I2C_ALGO_BITHS	0x130000	/* enhanced bit style adapters	*/
-#define I2C_ALGO_OCP_IOP3XX  0x140000	/* XSCALE IOP3XX On-chip I2C alg */
+#define I2C_ALGO_IOP3XX	0x140000	/* XSCALE IOP3XX On-chip I2C alg */
 #define I2C_ALGO_PCA	0x150000	/* PCA 9564 style adapters	*/
 
 #define I2C_ALGO_SIBYTE 0x150000	/* Broadcom SiByte SOCs		*/
@@ -270,7 +270,7 @@
 #define I2C_HW_SGI_MACE	0x01
 
 /* --- XSCALE on-chip adapters                          */
-#define I2C_HW_IOP321 0x00
+#define I2C_HW_IOP3XX 0x00
 
 /* --- SMBus only adapters						*/
 #define I2C_HW_SMBUS_PIIX4	0x00