Commit 5802c420 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman

ARM: dts: r8a7790: Convert to new CPG/MSSR bindings

Convert the R-Car H2 SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.

This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 2bd6bf03
...@@ -316,11 +316,8 @@ &du { ...@@ -316,11 +316,8 @@ &du {
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
clocks = <&mstp7_clks R8A7790_CLK_DU0>, clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
<&mstp7_clks R8A7790_CLK_DU1>, <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
<&mstp7_clks R8A7790_CLK_DU2>,
<&mstp7_clks R8A7790_CLK_LVDS0>,
<&mstp7_clks R8A7790_CLK_LVDS1>,
<&x13_clk>, <&x2_clk>; <&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
"dclkin.0", "dclkin.1"; "dclkin.0", "dclkin.1";
......
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