Commit 582d5fbd authored by Nicolas Ferre's avatar Nicolas Ferre

ARM: at91/pio: add new PIO3 features

This patch adds the support for new PIO controller found on some
at91sam SOCs.
- more peripheral multiplexing
- more features to configure on a PIO (pull-down, Schmitt trigger, debouncer)
- support for several IRQ triggering features (type and polarity)

Support for those new features are retrieved from the device tree
compatibility string.

Debugfs at91_gpio file is updated to monitor configuration.
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 9a9fe01e
* Atmel GPIO controller (PIO) * Atmel GPIO controller (PIO)
Required properties: Required properties:
- compatible: "atmel,at91rm9200-gpio" - compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
- reg: Should contain GPIO controller registers location and length - reg: Should contain GPIO controller registers location and length
- interrupts: Should be the port interrupt shared by all the pins. - interrupts: Should be the port interrupt shared by all the pins.
- #gpio-cells: Should be two. The first cell is the pin number and - #gpio-cells: Should be two. The first cell is the pin number and
......
...@@ -89,7 +89,7 @@ dma1: dma-controller@ffffee00 { ...@@ -89,7 +89,7 @@ dma1: dma-controller@ffffee00 {
}; };
pioA: gpio@fffff400 { pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x100>; reg = <0xfffff400 0x100>;
interrupts = <2 4>; interrupts = <2 4>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -98,7 +98,7 @@ pioA: gpio@fffff400 { ...@@ -98,7 +98,7 @@ pioA: gpio@fffff400 {
}; };
pioB: gpio@fffff600 { pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x100>; reg = <0xfffff600 0x100>;
interrupts = <2 4>; interrupts = <2 4>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -107,7 +107,7 @@ pioB: gpio@fffff600 { ...@@ -107,7 +107,7 @@ pioB: gpio@fffff600 {
}; };
pioC: gpio@fffff800 { pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x100>; reg = <0xfffff800 0x100>;
interrupts = <3 4>; interrupts = <3 4>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -116,7 +116,7 @@ pioC: gpio@fffff800 { ...@@ -116,7 +116,7 @@ pioC: gpio@fffff800 {
}; };
pioD: gpio@fffffa00 { pioD: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x100>; reg = <0xfffffa00 0x100>;
interrupts = <3 4>; interrupts = <3 4>;
#gpio-cells = <2>; #gpio-cells = <2>;
......
...@@ -86,6 +86,7 @@ static const struct of_device_id irq_of_match[] __initconst = { ...@@ -86,6 +86,7 @@ static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init }, { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
{ .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup }, { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
{ .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
{ /*sentinel*/ } { /*sentinel*/ }
}; };
......
This diff is collapsed.
...@@ -40,10 +40,35 @@ ...@@ -40,10 +40,35 @@
#define PIO_PUER 0x64 /* Pull-up Enable Register */ #define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */ #define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */ #define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
#define PIO_BSR 0x74 /* Peripheral B Select Register */ #define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
#define PIO_ABSR 0x78 /* AB Status Register */ #define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */ #define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */ #define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */ #define PIO_OWSR 0xa8 /* Output Write Status Register */
#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
#define PIO_ESR 0xc0 /* Edge Select Register */
#define PIO_LSR 0xc4 /* Level Select Register */
#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
#define ABCDSR_PERIPH_A 0x0
#define ABCDSR_PERIPH_B 0x1
#define ABCDSR_PERIPH_C 0x2
#define ABCDSR_PERIPH_D 0x3
#endif #endif
...@@ -191,10 +191,15 @@ ...@@ -191,10 +191,15 @@
extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup); extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
/* callable at any time */ /* callable at any time */
extern int at91_set_gpio_value(unsigned pin, int value); extern int at91_set_gpio_value(unsigned pin, int value);
......
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