Commit 588d511f authored by Anirudh Venkataramanan's avatar Anirudh Venkataramanan Committed by Jeff Kirsher

ice: Remove direct write for GLLAN_RCTL_0

Clear PXE mode AQ call (opcode 0x0110) is now supported in FW. So
remove the direct register write to GLLAN_RCTL_0.
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 95f8e8b9
...@@ -51,9 +51,6 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) ...@@ -51,9 +51,6 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)
*/ */
void ice_dev_onetime_setup(struct ice_hw *hw) void ice_dev_onetime_setup(struct ice_hw *hw)
{ {
/* configure Rx - set non pxe mode */
wr32(hw, GLLAN_RCTL_0, 0x1);
#define MBX_PF_VT_PFALLOC 0x00231E80 #define MBX_PF_VT_PFALLOC 0x00231E80
/* set VFs per PF */ /* set VFs per PF */
wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF)); wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF));
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment