Commit 58b278f5 authored by Vaibhav Jain's avatar Vaibhav Jain Committed by Michael Ellerman

powerpc: Provide initial documentation for PAPR hcalls

This doc patch provides an initial description of the hcall op-codes
that are used by Linux kernel running as a guest (LPAR) on top of
PowerVM or any other sPAPR compliant hyper-visor (e.g qemu).

Apart from documenting the hcalls the doc-patch also provides a
rudimentary overview of how hcall ABI, how they are issued with the
Linux kernel and how information/control flows between the guest and
hypervisor.
Signed-off-by: default avatarVaibhav Jain <vaibhav@linux.ibm.com>
Reviewed-by: default avatarLaurent Dufour <ldufour@linux.ibm.com>
Acked-by: default avatarNicholas Piggin <npiggin@gmail.com>
[mpe: Add SPDX tag, add it to index.rst]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190828082729.16695-1-vaibhav@linux.ibm.com
parent 99338190
...@@ -22,6 +22,7 @@ powerpc ...@@ -22,6 +22,7 @@ powerpc
isa-versions isa-versions
kaslr-booke32 kaslr-booke32
mpc52xx mpc52xx
papr_hcalls
pci_iov_resource_on_powernv pci_iov_resource_on_powernv
pmu-ebb pmu-ebb
ptrace ptrace
......
This diff is collapsed.
...@@ -1408,22 +1408,9 @@ EXC_VIRT_NONE(0x4b00, 0x100) ...@@ -1408,22 +1408,9 @@ EXC_VIRT_NONE(0x4b00, 0x100)
* *
* Call convention: * Call convention:
* *
* syscall register convention is in Documentation/powerpc/syscall64-abi.rst * syscall and hypercalls register conventions are documented in
* * Documentation/powerpc/syscall64-abi.rst and
* For hypercalls, the register convention is as follows: * Documentation/powerpc/papr_hcalls.rst respectively.
* r0 volatile
* r1-2 nonvolatile
* r3 volatile parameter and return value for status
* r4-r10 volatile input and output value
* r11 volatile hypercall number and output value
* r12 volatile input and output value
* r13-r31 nonvolatile
* LR nonvolatile
* CTR volatile
* XER volatile
* CR0-1 CR5-7 volatile
* CR2-4 nonvolatile
* Other registers nonvolatile
* *
* The intersection of volatile registers that don't contain possible * The intersection of volatile registers that don't contain possible
* inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
......
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