Commit 59d05b51 authored by Shawn Guo's avatar Shawn Guo

ARM: imx: fix TLB missing of IOMUXC base address during suspend

After the suspend routine running in OCRAM puts DDR into self-refresh,
it will access IOMUXC block to float DDR IO for power saving.  A TLB
missing of IOMUXC base address may happen in this case, and triggers an
access to DDR, and thus hangs the system.

The failure is discovered by running suspend/resume on a Cubox-i board.
Though the issue is not Cubox-i specific, it can be hit the on the board
quite easily with the 3.15 or 3.16 kernel.

Fix the issue with a dummy access to IOMUXC block at the beginning of
suspend routine, so that the address translation can be filled into TLB
before DDR is put into self-refresh.
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
Cc: <stable@vger.kernel.org>
Acked-by: default avatarAnson Huang <Anson.Huang@freescale.com>
parent 060d517d
...@@ -173,6 +173,8 @@ ENTRY(imx6_suspend) ...@@ -173,6 +173,8 @@ ENTRY(imx6_suspend)
ldr r6, [r11, #0x0] ldr r6, [r11, #0x0]
ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
ldr r6, [r11, #0x0] ldr r6, [r11, #0x0]
ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
ldr r6, [r11, #0x0]
/* use r11 to store the IO address */ /* use r11 to store the IO address */
ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
......
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