Commit 5a2ae95e authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter

drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A

Also make the WA comment consistent with the rest, where the stepping
info is not shown.
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6c0fd451
...@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) ...@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE); GEN9_CCS_TLB_PREFETCH_ENABLE);
/* /* WaDisableMaskBasedCammingInRCC:skl,bxt */
* FIXME: don't apply the following on BXT for stepping C. On BXT A0 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
* the flag reads back as 0. (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
*/
/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE); PIXEL_MASK_CAMMING_DISABLE);
......
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