Commit 5ac072e1 authored by Kuninori Morimoto's avatar Kuninori Morimoto Committed by Paul Mundt

sh: Urquell board support.

This adds preliminary support for the SH7786-based Urquell board.
Signed-off-by: default avatarKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 37042fbd
...@@ -162,6 +162,11 @@ config SH_SH7785LCR_29BIT_PHYSMAPS ...@@ -162,6 +162,11 @@ config SH_SH7785LCR_29BIT_PHYSMAPS
DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
you can access all on-board device in 29bit address mode. you can access all on-board device in 29bit address mode.
config SH_URQUELL
bool "Urquell"
depends on CPU_SUBTYPE_SH7786
select ARCH_REQUIRE_GPIOLIB
config SH_MIGOR config SH_MIGOR
bool "Migo-R" bool "Migo-R"
depends on CPU_SUBTYPE_SH7722 depends on CPU_SUBTYPE_SH7722
......
...@@ -4,5 +4,6 @@ ...@@ -4,5 +4,6 @@
obj-$(CONFIG_SH_AP325RXA) += board-ap325rxa.o obj-$(CONFIG_SH_AP325RXA) += board-ap325rxa.o
obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o
obj-$(CONFIG_SH_URQUELL) += board-urquell.o
obj-$(CONFIG_SH_SHMIN) += board-shmin.o obj-$(CONFIG_SH_SHMIN) += board-shmin.o
obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o
/*
* Renesas Technology Corp. SH7786 Urquell Support.
*
* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
* Copyright (C) 2008 Yoshihiro Shimoda
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <mach/urquell.h>
#include <cpu/sh7786.h>
#include <asm/heartbeat.h>
#include <asm/sizes.h>
static struct resource heartbeat_resources[] = {
[0] = {
.start = BOARDREG(SLEDR),
.end = BOARDREG(SLEDR),
.flags = IORESOURCE_MEM,
},
};
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "loader",
.offset = 0x00000000,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE, /* Read-only */
},
{
.name = "bootenv",
.offset = MTDPART_OFS_APPEND,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE, /* Read-only */
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
},
{
.name = "data",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 2,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
static struct resource nor_flash_resources[] = {
[0] = {
.start = NOR_FLASH_ADDR,
.end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.dev = {
.platform_data = &nor_flash_data,
},
.num_resources = ARRAY_SIZE(nor_flash_resources),
.resource = nor_flash_resources,
};
static struct platform_device *urquell_devices[] __initdata = {
&heartbeat_device,
&nor_flash_device,
};
static int __init urquell_devices_setup(void)
{
/* USB */
gpio_request(GPIO_FN_USB_OVC0, NULL);
gpio_request(GPIO_FN_USB_PENC0, NULL);
return platform_add_devices(urquell_devices,
ARRAY_SIZE(urquell_devices));
}
device_initcall(urquell_devices_setup);
static void urquell_power_off(void)
{
__raw_writew(0xa5a5, UBOARDREG(SRSTR));
}
/* Initialize the board */
static void __init urquell_setup(char **cmdline_p)
{
printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
pm_power_off = urquell_power_off;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_urquell __initmv = {
.mv_name = "Urquell",
.mv_setup = urquell_setup,
};
This diff is collapsed.
#ifndef __MACH_URQUELL_H
#define __MACH_URQUELL_H
/*
* ------ 0x00000000 ------------------------------------
* CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH
* -----+ 0x04000000 ------------------------------------
* CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH
* -----+ 0x08000000 ------------------------------------
* CS2 | DDR3
* CS3 |
* -----+ 0x10000000 ------------------------------------
* CS4 | PCIe
* -----+ 0x14000000 ------------------------------------
* CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA
* -----+ 0x18000000 ------------------------------------
* CS6 | ATA, NAND FLASH
* -----+ 0x1c000000 ------------------------------------
* CS7 | SH7786 register
* -----+------------------------------------------------
*/
#define NOR_FLASH_ADDR 0x00000000
#define NOR_FLASH_SIZE 0x04000000
#define CS1_BASE 0x05000000
#define CS5_BASE 0x15000000
#define FPGA_BASE CS1_BASE
#define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS)
#define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS)
#define SRSTR_OFS 0x0000 /* System reset register */
#define BDMR_OFS 0x0010 /* Board operating mode resister */
#define IRL0SR_OFS 0x0020 /* IRL0 Status register */
#define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */
#define IRL1SR_OFS 0x0040 /* IRL1 Status register */
#define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */
#define IRL2SR_OFS 0x0060 /* IRL2 Status register */
#define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */
#define IRL3SR_OFS 0x0080 /* IRL3 Status register */
#define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */
#define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */
#define SLEDR_OFS 0x0130 /* LED control resister */
#define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */
#define FPVERR_OFS 0x0150 /* FPGA Version register */
#define FPDATER_OFS 0x0160 /* FPGA Date register */
#define FPYEARR_OFS 0x0170 /* FPGA Year register */
#define TCLKCR_OFS 0x0180 /* TCLK Control register */
#define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */
#define FPODR_OFS 0x1010 /* Output port data register */
#define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */
#define FPINDR_OFS 0x1030 /* Input port data register */
#define MDSWMR_OFS 0x1040 /* MODE SW monitor register */
#define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */
#define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */
#define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */
#define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */
#define LATCHCR_OFS 0x3000 /* Latch control register */
#define LATCUAR_OFS 0x3010 /* Latch upper address register */
#define LATCLAR_OFS 0x3012 /* Latch lower address register */
#define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
#define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
#define CHARLED_OFS 0x2000 /* Character LED */
#endif /* __MACH_URQUELL_H */
...@@ -52,3 +52,4 @@ RSK7203 SH_RSK7203 ...@@ -52,3 +52,4 @@ RSK7203 SH_RSK7203
AP325RXA SH_AP325RXA AP325RXA SH_AP325RXA
SH7763RDP SH_SH7763RDP SH7763RDP SH_SH7763RDP
SH7785LCR SH_SH7785LCR SH7785LCR SH_SH7785LCR
URQUELL SH_URQUELL
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