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Commit 5ae13ef4 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'regmap-3.11' of git://git.infradead.org/users/jcooper/linux into next/soc 

mvebu register map changes for v3.11

This series removes the hardcoded register base address for mvebu.

Depends:
 - mvebu/fixes-non-critical (up to tags/fixes-non-3.11-1)
 - mvebu/cleanup (up to tags/cleanup-3.11-3)

* tag 'regmap-3.11' of git://git.infradead.org/users/jcooper/linux:
  arm: mvebu: disable DEBUG_LL/EARLY_PRINTK in defconfig
  arm: mvebu: add another earlyprintk Kconfig option
  arm: mvebu: don't hardcode the physical address for mvebu-mbus
  arm: mvebu: don't hardcode a physical address in headsmp.S
  arm: mvebu: remove hardcoded static I/O mapping
  arm: mvebu: move cache and mvebu-mbus initialization later
  arm: mvebu: avoid hardcoded virtual address in coherency code
  arm: mvebu: remove dependency of SMP init on static I/O mapping
  arm: mvebu: fix length of Ethernet registers area in .dtsi
  arm: mvebu: fix length of SATA registers area in .dtsi
  arm: mvebu: mark functions of armada-370-xp.c as static
  ARM: mvebu: Remove init_irq declaration in machine description
  ARM: Orion: Remove redundant init_dma_coherent_pool_size()
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 01758fe6 5fb2038d
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Showing with 107 additions and 81 deletions
arch/arm/Kconfig.debug
View file @ 5ae13ef4
......@@ -303,12 +303,37 @@ choice
their output to the serial port on MSM 8960 devices.
config DEBUG_MVEBU_UART
bool "Kernel low-level debugging messages via MVEBU UART"
bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
depends on ARCH_MVEBU
help
Say Y here if you want kernel low-level debugging support
on MVEBU based platforms.
This option should be used with the old bootloaders
that left the internal registers mapped at
0xd0000000. As of today, this is the case on
platforms such as the Globalscale Mirabox or the
Plathome OpenBlocks AX3, when using the original
bootloader.
If the wrong DEBUG_MVEBU_UART* option is selected,
when u-boot hands over to the kernel, the system
silently crashes, with no serial output at all.
config DEBUG_MVEBU_UART_ALTERNATE
bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
depends on ARCH_MVEBU
help
Say Y here if you want kernel low-level debugging support
on MVEBU based platforms.
This option should be used with the new bootloaders
that remap the internal registers at 0xf1000000.
If the wrong DEBUG_MVEBU_UART* option is selected,
when u-boot hands over to the kernel, the system
silently crashes, with no serial output at all.
config DEBUG_NOMADIK_UART
bool "Kernel low-level debugging messages via NOMADIK UART"
depends on ARCH_NOMADIK
......@@ -632,7 +657,8 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART ||\
DEBUG_IMX6Q_UART
default "debug/mvebu.S" if DEBUG_MVEBU_UART
default "debug/mvebu.S" if DEBUG_MVEBU_UART || \
DEBUG_MVEBU_UART_ALTERNATE
default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default "debug/nomadik.S" if DEBUG_NOMADIK_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
......
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ 5ae13ef4
......@@ -80,7 +80,7 @@ timer@20300 {
sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x2400>;
reg = <0xa0000 0x5000>;
interrupts = <55>;
clocks = <&gateclk 15>, <&gateclk 30>;
clock-names = "0", "1";
......@@ -96,7 +96,7 @@ mdio {
ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x2500>;
reg = <0x70000 0x4000>;
interrupts = <8>;
clocks = <&gateclk 4>;
status = "disabled";
......@@ -104,7 +104,7 @@ ethernet@70000 {
ethernet@74000 {
compatible = "marvell,armada-370-neta";
reg = <0x74000 0x2500>;
reg = <0x74000 0x4000>;
interrupts = <10>;
clocks = <&gateclk 3>;
status = "disabled";
......
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View file @ 5ae13ef4
......@@ -107,7 +107,7 @@ gpio2: gpio@18180 {
ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x2500>;
reg = <0x34000 0x4000>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
......
arch/arm/boot/dts/armada-xp.dtsi
View file @ 5ae13ef4
......@@ -88,7 +88,7 @@ system-controller@18200 {
ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x2500>;
reg = <0x30000 0x4000>;
interrupts = <12>;
clocks = <&gateclk 2>;
status = "disabled";
......
arch/arm/configs/mvebu_defconfig
View file @ 5ae13ef4
......@@ -100,5 +100,3 @@ CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
arch/arm/include/debug/mvebu.S
View file @ 5ae13ef4
......@@ -11,7 +11,12 @@
* published by the Free Software Foundation.
*/
#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000
#else
#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
#endif
#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000
.macro addruart, rp, rv, tmp
......
arch/arm/mach-mvebu/armada-370-xp.c
View file @ 5ae13ef4
......@@ -15,12 +15,12 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/time-armada-370-xp.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <linux/irqchip.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -29,45 +29,49 @@
#include "common.h"
#include "coherency.h"
static struct map_desc armada_370_xp_io_desc[] __initdata = {
{
.virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
.length = ARMADA_370_XP_REGS_SIZE,
.type = MT_DEVICE,
},
};
void __init armada_370_xp_map_io(void)
static void __init armada_370_xp_map_io(void)
{
iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
debug_ll_io_init();
}
void __init armada_370_xp_timer_and_clk_init(void)
{
of_clk_init(NULL);
armada_370_xp_timer_init();
}
/*
* This initialization will be replaced by a DT-based
* initialization once the mvebu-mbus driver gains DT support.
*/
void __init armada_370_xp_init_early(void)
#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
static void __init armada_370_xp_mbus_init(void)
{
char *mbus_soc_name;
struct device_node *dn;
const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
/*
* This initialization will be replaced by a DT-based
* initialization once the mvebu-mbus driver gains DT support.
*/
if (of_machine_is_compatible("marvell,armada370"))
mbus_soc_name = "marvell,armada370-mbus";
else
mbus_soc_name = "marvell,armadaxp-mbus";
dn = of_find_node_by_name(NULL, "internal-regs");
BUG_ON(!dn);
mvebu_mbus_init(mbus_soc_name,
ARMADA_370_XP_MBUS_WINS_BASE,
of_translate_address(dn, &mbus_wins_offs),
ARMADA_370_XP_MBUS_WINS_SIZE,
ARMADA_370_XP_SDRAM_WINS_BASE,
of_translate_address(dn, &sdram_wins_offs),
ARMADA_370_XP_SDRAM_WINS_SIZE);
}
static void __init armada_370_xp_timer_and_clk_init(void)
{
of_clk_init(NULL);
armada_370_xp_timer_init();
coherency_init();
armada_370_xp_mbus_init();
#ifdef CONFIG_CACHE_L2X0
l2x0_of_init(0, ~0UL);
#endif
......@@ -76,7 +80,6 @@ void __init armada_370_xp_init_early(void)
static void __init armada_370_xp_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
coherency_init();
}
static const char * const armada_370_xp_dt_compat[] = {
......@@ -88,8 +91,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
.smp = smp_ops(armada_xp_smp_ops),
.init_machine = armada_370_xp_dt_init,
.map_io = armada_370_xp_map_io,
.init_early = armada_370_xp_init_early,
.init_irq = irqchip_init,
.init_time = armada_370_xp_timer_and_clk_init,
.restart = mvebu_restart,
.dt_compat = armada_370_xp_dt_compat,
......
arch/arm/mach-mvebu/armada-370-xp.h
View file @ 5ae13ef4
......@@ -15,16 +15,6 @@
#ifndef __MACH_ARMADA_370_XP_H
#define __MACH_ARMADA_370_XP_H
#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000)
#define ARMADA_370_XP_REGS_SIZE SZ_1M
/* These defines can go away once mvebu-mbus has a DT binding */
#define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
#define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
#ifdef CONFIG_SMP
#include <linux/cpumask.h>
......
arch/arm/mach-mvebu/coherency.c
View file @ 5ae13ef4
......@@ -25,16 +25,11 @@
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include "armada-370-xp.h"
/*
* Some functions in this file are called very early during SMP
* initialization. At that time the device tree framework is not yet
* ready, and it is not possible to get the register address to
* ioremap it. That's why the pointer below is given with an initial
* value matching its virtual mapping
*/
static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
unsigned long __cpuinitdata coherency_phys_base;
static void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;
/* Coherency fabric registers */
......@@ -47,18 +42,6 @@ static struct of_device_id of_coherency_table[] = {
{ /* end of list */ },
};
#ifdef CONFIG_SMP
int coherency_get_cpu_count(void)
{
int reg, cnt;
reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
cnt = (reg & 0xF) + 1;
return cnt;
}
#endif
/* Function defined in coherency_ll.S */
int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
......@@ -143,13 +126,30 @@ int __init coherency_init(void)
np = of_find_matching_node(NULL, of_coherency_table);
if (np) {
struct resource res;
pr_info("Initializing Coherency fabric\n");
of_address_to_resource(np, 0, &res);
coherency_phys_base = res.start;
/*
* Ensure secondary CPUs will see the updated value,
* which they read before they join the coherency
* fabric, and therefore before they are coherent with
* the boot CPU cache.
*/
sync_cache_w(&coherency_phys_base);
coherency_base = of_iomap(np, 0);
coherency_cpu_base = of_iomap(np, 1);
set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
bus_register_notifier(&platform_bus_type,
&mvebu_hwcc_platform_nb);
}
return 0;
}
static int __init coherency_late_init(void)
{
bus_register_notifier(&platform_bus_type,
&mvebu_hwcc_platform_nb);
return 0;
}
postcore_initcall(coherency_late_init);
arch/arm/mach-mvebu/coherency.h
View file @ 5ae13ef4
......@@ -14,10 +14,6 @@
#ifndef __MACH_370_XP_COHERENCY_H
#define __MACH_370_XP_COHERENCY_H
#ifdef CONFIG_SMP
int coherency_get_cpu_count(void);
#endif
int set_cpu_coherent(int cpu_id, int smp_group_id);
int coherency_init(void);
......
arch/arm/mach-mvebu/common.h
View file @ 5ae13ef4
......@@ -15,6 +15,8 @@
#ifndef __ARCH_MVEBU_COMMON_H
#define __ARCH_MVEBU_COMMON_H
#define ARMADA_XP_MAX_CPUS 4
void mvebu_restart(char mode, const char *cmd);
void armada_370_xp_init_irq(void);
......
arch/arm/mach-mvebu/headsmp.S
View file @ 5ae13ef4
......@@ -21,12 +21,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
/*
* At this stage the secondary CPUs don't have acces yet to the MMU, so
* we have to provide physical addresses
*/
#define ARMADA_XP_CFB_BASE 0xD0020200
__CPUINIT
/*
......@@ -35,15 +29,21 @@
* startup
*/
ENTRY(armada_xp_secondary_startup)
/* Get coherency fabric base physical address */
adr r0, 1f
ldr r1, [r0]
ldr r0, [r0, r1]
/* Read CPU id */
mrc p15, 0, r1, c0, c0, 5
and r1, r1, #0xF
/* Add CPU to coherency fabric */
ldr r0, =ARMADA_XP_CFB_BASE
bl ll_set_cpu_coherent
b secondary_startup
ENDPROC(armada_xp_secondary_startup)
.align 2
1:
.long coherency_phys_base - .
arch/arm/mach-mvebu/platsmp.c
View file @ 5ae13ef4
......@@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
static void __init armada_xp_smp_init_cpus(void)
{
struct device_node *np;
unsigned int i, ncores;
ncores = coherency_get_cpu_count();
np = of_find_node_by_name(NULL, "cpus");
if (!np)
panic("No 'cpus' node found\n");
ncores = of_get_child_count(np);
if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
panic("Invalid number of CPUs in DT\n");
/* Limit possible CPUs to defconfig */
if (ncores > nr_cpu_ids) {
......
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