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Commit 5b0c189f authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/bar: cosmetic changes 

This is purely preparation for upcoming commits, there should be no
code changes here.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 9ace404b
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Showing with 127 additions and 135 deletions
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
View file @ 5b0c189f
...@@ -5,7 +5,7 @@ struct nvkm_mem; ...@@ -5,7 +5,7 @@ struct nvkm_mem;
struct nvkm_vma; struct nvkm_vma;
struct nvkm_bar { struct nvkm_bar {
struct nvkm_subdev base; struct nvkm_subdev subdev;
int (*alloc)(struct nvkm_bar *, struct nvkm_object *, int (*alloc)(struct nvkm_bar *, struct nvkm_object *,
struct nvkm_mem *, struct nvkm_object **); struct nvkm_mem *, struct nvkm_object **);
......
drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
View file @ 5b0c189f
...@@ -117,22 +117,14 @@ int ...@@ -117,22 +117,14 @@ int
nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, int length, void **pobject) struct nvkm_oclass *oclass, int length, void **pobject)
{ {
struct nvkm_bar *bar; return nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL",
int ret; "bar", length, pobject);
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL",
"bar", length, pobject);
bar = *pobject;
if (ret)
return ret;
return 0;
} }
void void
nvkm_bar_destroy(struct nvkm_bar *bar) nvkm_bar_destroy(struct nvkm_bar *bar)
{ {
nvkm_subdev_destroy(&bar->base); nvkm_subdev_destroy(&bar->subdev);
} }
void void
......
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
View file @ 5b0c189f
...@@ -27,26 +27,26 @@ ...@@ -27,26 +27,26 @@
#include <subdev/fb.h> #include <subdev/fb.h>
#include <subdev/mmu.h> #include <subdev/mmu.h>
struct gf100_bar_priv_vm { struct gf100_bar_vm {
struct nvkm_gpuobj *mem; struct nvkm_gpuobj *mem;
struct nvkm_gpuobj *pgd; struct nvkm_gpuobj *pgd;
struct nvkm_vm *vm; struct nvkm_vm *vm;
}; };
struct gf100_bar_priv { struct gf100_bar {
struct nvkm_bar base; struct nvkm_bar base;
spinlock_t lock; spinlock_t lock;
struct gf100_bar_priv_vm bar[2]; struct gf100_bar_vm bar[2];
}; };
static int static int
gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, gf100_bar_kmap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
struct nvkm_vma *vma) struct nvkm_vma *vma)
{ {
struct gf100_bar_priv *priv = (void *)bar; struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
int ret; int ret;
ret = nvkm_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma); ret = nvkm_vm_get(bar->bar[0].vm, mem->size << 12, 12, flags, vma);
if (ret) if (ret)
return ret; return ret;
...@@ -55,13 +55,13 @@ gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, ...@@ -55,13 +55,13 @@ gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
} }
static int static int
gf100_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, gf100_bar_umap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
struct nvkm_vma *vma) struct nvkm_vma *vma)
{ {
struct gf100_bar_priv *priv = (void *)bar; struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
int ret; int ret;
ret = nvkm_vm_get(priv->bar[1].vm, mem->size << 12, ret = nvkm_vm_get(bar->bar[1].vm, mem->size << 12,
mem->page_shift, flags, vma); mem->page_shift, flags, vma);
if (ret) if (ret)
return ret; return ret;
...@@ -78,20 +78,20 @@ gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) ...@@ -78,20 +78,20 @@ gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
} }
static int static int
gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm, gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
int bar_nr) int bar_nr)
{ {
struct nvkm_device *device = nv_device(&priv->base); struct nvkm_device *device = nv_device(&bar->base);
struct nvkm_vm *vm; struct nvkm_vm *vm;
resource_size_t bar_len; resource_size_t bar_len;
int ret; int ret;
ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x1000, 0, 0,
&bar_vm->mem); &bar_vm->mem);
if (ret) if (ret)
return ret; return ret;
ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x8000, 0, 0,
&bar_vm->pgd); &bar_vm->pgd);
if (ret) if (ret)
return ret; return ret;
...@@ -108,7 +108,7 @@ gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm, ...@@ -108,7 +108,7 @@ gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm,
* Bootstrap page table lookup. * Bootstrap page table lookup.
*/ */
if (bar_nr == 3) { if (bar_nr == 3) {
ret = nvkm_gpuobj_new(nv_object(priv), NULL, ret = nvkm_gpuobj_new(nv_object(bar), NULL,
(bar_len >> 12) * 8, 0x1000, (bar_len >> 12) * 8, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC, NVOBJ_FLAG_ZERO_ALLOC,
&vm->pgt[0].obj[0]); &vm->pgt[0].obj[0]);
...@@ -135,74 +135,74 @@ gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ...@@ -135,74 +135,74 @@ gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct nvkm_device *device = nv_device(parent); struct nvkm_device *device = nv_device(parent);
struct gf100_bar_priv *priv; struct gf100_bar *bar;
bool has_bar3 = nv_device_resource_len(device, 3) != 0; bool has_bar3 = nv_device_resource_len(device, 3) != 0;
int ret; int ret;
ret = nvkm_bar_create(parent, engine, oclass, &priv); ret = nvkm_bar_create(parent, engine, oclass, &bar);
*pobject = nv_object(priv); *pobject = nv_object(bar);
if (ret) if (ret)
return ret; return ret;
/* BAR3 */ /* BAR3 */
if (has_bar3) { if (has_bar3) {
ret = gf100_bar_ctor_vm(priv, &priv->bar[0], 3); ret = gf100_bar_ctor_vm(bar, &bar->bar[0], 3);
if (ret) if (ret)
return ret; return ret;
} }
/* BAR1 */ /* BAR1 */
ret = gf100_bar_ctor_vm(priv, &priv->bar[1], 1); ret = gf100_bar_ctor_vm(bar, &bar->bar[1], 1);
if (ret) if (ret)
return ret; return ret;
if (has_bar3) { if (has_bar3) {
priv->base.alloc = nvkm_bar_alloc; bar->base.alloc = nvkm_bar_alloc;
priv->base.kmap = gf100_bar_kmap; bar->base.kmap = gf100_bar_kmap;
} }
priv->base.umap = gf100_bar_umap; bar->base.umap = gf100_bar_umap;
priv->base.unmap = gf100_bar_unmap; bar->base.unmap = gf100_bar_unmap;
priv->base.flush = g84_bar_flush; bar->base.flush = g84_bar_flush;
spin_lock_init(&priv->lock); spin_lock_init(&bar->lock);
return 0; return 0;
} }
void void
gf100_bar_dtor(struct nvkm_object *object) gf100_bar_dtor(struct nvkm_object *object)
{ {
struct gf100_bar_priv *priv = (void *)object; struct gf100_bar *bar = (void *)object;
nvkm_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd); nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd);
nvkm_gpuobj_ref(NULL, &priv->bar[1].pgd); nvkm_gpuobj_ref(NULL, &bar->bar[1].pgd);
nvkm_gpuobj_ref(NULL, &priv->bar[1].mem); nvkm_gpuobj_ref(NULL, &bar->bar[1].mem);
if (priv->bar[0].vm) { if (bar->bar[0].vm) {
nvkm_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); nvkm_gpuobj_ref(NULL, &bar->bar[0].vm->pgt[0].obj[0]);
nvkm_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd);
} }
nvkm_gpuobj_ref(NULL, &priv->bar[0].pgd); nvkm_gpuobj_ref(NULL, &bar->bar[0].pgd);
nvkm_gpuobj_ref(NULL, &priv->bar[0].mem); nvkm_gpuobj_ref(NULL, &bar->bar[0].mem);
nvkm_bar_destroy(&priv->base); nvkm_bar_destroy(&bar->base);
} }
int int
gf100_bar_init(struct nvkm_object *object) gf100_bar_init(struct nvkm_object *object)
{ {
struct gf100_bar_priv *priv = (void *)object; struct gf100_bar *bar = (void *)object;
int ret; int ret;
ret = nvkm_bar_init(&priv->base); ret = nvkm_bar_init(&bar->base);
if (ret) if (ret)
return ret; return ret;
nv_mask(priv, 0x000200, 0x00000100, 0x00000000); nv_mask(bar, 0x000200, 0x00000100, 0x00000000);
nv_mask(priv, 0x000200, 0x00000100, 0x00000100); nv_mask(bar, 0x000200, 0x00000100, 0x00000100);
nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); nv_wr32(bar, 0x001704, 0x80000000 | bar->bar[1].mem->addr >> 12);
if (priv->bar[0].mem) if (bar->bar[0].mem)
nv_wr32(priv, 0x001714, nv_wr32(bar, 0x001714,
0xc0000000 | priv->bar[0].mem->addr >> 12); 0xc0000000 | bar->bar[0].mem->addr >> 12);
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
View file @ 5b0c189f
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#include <subdev/mmu.h> #include <subdev/mmu.h>
#include <subdev/timer.h> #include <subdev/timer.h>
struct nv50_bar_priv { struct nv50_bar {
struct nvkm_bar base; struct nvkm_bar base;
spinlock_t lock; spinlock_t lock;
struct nvkm_gpuobj *mem; struct nvkm_gpuobj *mem;
...@@ -41,13 +41,13 @@ struct nv50_bar_priv { ...@@ -41,13 +41,13 @@ struct nv50_bar_priv {
}; };
static int static int
nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, nv50_bar_kmap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
struct nvkm_vma *vma) struct nvkm_vma *vma)
{ {
struct nv50_bar_priv *priv = (void *)bar; struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
int ret; int ret;
ret = nvkm_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma); ret = nvkm_vm_get(bar->bar3_vm, mem->size << 12, 12, flags, vma);
if (ret) if (ret)
return ret; return ret;
...@@ -56,13 +56,13 @@ nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, ...@@ -56,13 +56,13 @@ nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
} }
static int static int
nv50_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, nv50_bar_umap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
struct nvkm_vma *vma) struct nvkm_vma *vma)
{ {
struct nv50_bar_priv *priv = (void *)bar; struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
int ret; int ret;
ret = nvkm_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma); ret = nvkm_vm_get(bar->bar1_vm, mem->size << 12, 12, flags, vma);
if (ret) if (ret)
return ret; return ret;
...@@ -78,27 +78,27 @@ nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) ...@@ -78,27 +78,27 @@ nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
} }
static void static void
nv50_bar_flush(struct nvkm_bar *bar) nv50_bar_flush(struct nvkm_bar *obj)
{ {
struct nv50_bar_priv *priv = (void *)bar; struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&bar->lock, flags);
nv_wr32(priv, 0x00330c, 0x00000001); nv_wr32(bar, 0x00330c, 0x00000001);
if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000)) if (!nv_wait(bar, 0x00330c, 0x00000002, 0x00000000))
nv_warn(priv, "flush timeout\n"); nv_warn(bar, "flush timeout\n");
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&bar->lock, flags);
} }
void void
g84_bar_flush(struct nvkm_bar *bar) g84_bar_flush(struct nvkm_bar *obj)
{ {
struct nv50_bar_priv *priv = (void *)bar; struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&bar->lock, flags);
nv_wr32(bar, 0x070000, 0x00000001); nv_wr32(bar, 0x070000, 0x00000001);
if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000)) if (!nv_wait(bar, 0x070000, 0x00000002, 0x00000000))
nv_warn(priv, "flush timeout\n"); nv_warn(bar, "flush timeout\n");
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&bar->lock, flags);
} }
static int static int
...@@ -109,28 +109,28 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ...@@ -109,28 +109,28 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_device *device = nv_device(parent); struct nvkm_device *device = nv_device(parent);
struct nvkm_object *heap; struct nvkm_object *heap;
struct nvkm_vm *vm; struct nvkm_vm *vm;
struct nv50_bar_priv *priv; struct nv50_bar *bar;
u64 start, limit; u64 start, limit;
int ret; int ret;
ret = nvkm_bar_create(parent, engine, oclass, &priv); ret = nvkm_bar_create(parent, engine, oclass, &bar);
*pobject = nv_object(priv); *pobject = nv_object(bar);
if (ret) if (ret)
return ret; return ret;
ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x20000, 0,
NVOBJ_FLAG_HEAP, &priv->mem); NVOBJ_FLAG_HEAP, &bar->mem);
heap = nv_object(priv->mem); heap = nv_object(bar->mem);
if (ret) if (ret)
return ret; return ret;
ret = nvkm_gpuobj_new(nv_object(priv), heap, ret = nvkm_gpuobj_new(nv_object(bar), heap,
(device->chipset == 0x50) ? 0x1400 : 0x0200, (device->chipset == 0x50) ? 0x1400 : 0x0200,
0, 0, &priv->pad); 0, 0, &bar->pad);
if (ret) if (ret)
return ret; return ret;
ret = nvkm_gpuobj_new(nv_object(priv), heap, 0x4000, 0, 0, &priv->pgd); ret = nvkm_gpuobj_new(nv_object(bar), heap, 0x4000, 0, 0, &bar->pgd);
if (ret) if (ret)
return ret; return ret;
...@@ -144,29 +144,29 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ...@@ -144,29 +144,29 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
ret = nvkm_gpuobj_new(nv_object(priv), heap, ret = nvkm_gpuobj_new(nv_object(bar), heap,
((limit-- - start) >> 12) * 8, 0x1000, ((limit-- - start) >> 12) * 8, 0x1000,
NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
vm->pgt[0].refcount[0] = 1; vm->pgt[0].refcount[0] = 1;
if (ret) if (ret)
return ret; return ret;
ret = nvkm_vm_ref(vm, &priv->bar3_vm, priv->pgd); ret = nvkm_vm_ref(vm, &bar->bar3_vm, bar->pgd);
nvkm_vm_ref(NULL, &vm, NULL); nvkm_vm_ref(NULL, &vm, NULL);
if (ret) if (ret)
return ret; return ret;
ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3); ret = nvkm_gpuobj_new(nv_object(bar), heap, 24, 16, 0, &bar->bar3);
if (ret) if (ret)
return ret; return ret;
nv_wo32(priv->bar3, 0x00, 0x7fc00000); nv_wo32(bar->bar3, 0x00, 0x7fc00000);
nv_wo32(priv->bar3, 0x04, lower_32_bits(limit)); nv_wo32(bar->bar3, 0x04, lower_32_bits(limit));
nv_wo32(priv->bar3, 0x08, lower_32_bits(start)); nv_wo32(bar->bar3, 0x08, lower_32_bits(start));
nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 | nv_wo32(bar->bar3, 0x0c, upper_32_bits(limit) << 24 |
upper_32_bits(start)); upper_32_bits(start));
nv_wo32(priv->bar3, 0x10, 0x00000000); nv_wo32(bar->bar3, 0x10, 0x00000000);
nv_wo32(priv->bar3, 0x14, 0x00000000); nv_wo32(bar->bar3, 0x14, 0x00000000);
/* BAR1 */ /* BAR1 */
start = 0x0000000000ULL; start = 0x0000000000ULL;
...@@ -178,84 +178,84 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ...@@ -178,84 +178,84 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
ret = nvkm_vm_ref(vm, &priv->bar1_vm, priv->pgd); ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd);
nvkm_vm_ref(NULL, &vm, NULL); nvkm_vm_ref(NULL, &vm, NULL);
if (ret) if (ret)
return ret; return ret;
ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1); ret = nvkm_gpuobj_new(nv_object(bar), heap, 24, 16, 0, &bar->bar1);
if (ret) if (ret)
return ret; return ret;
nv_wo32(priv->bar1, 0x00, 0x7fc00000); nv_wo32(bar->bar1, 0x00, 0x7fc00000);
nv_wo32(priv->bar1, 0x04, lower_32_bits(limit)); nv_wo32(bar->bar1, 0x04, lower_32_bits(limit));
nv_wo32(priv->bar1, 0x08, lower_32_bits(start)); nv_wo32(bar->bar1, 0x08, lower_32_bits(start));
nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 | nv_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |
upper_32_bits(start)); upper_32_bits(start));
nv_wo32(priv->bar1, 0x10, 0x00000000); nv_wo32(bar->bar1, 0x10, 0x00000000);
nv_wo32(priv->bar1, 0x14, 0x00000000); nv_wo32(bar->bar1, 0x14, 0x00000000);
priv->base.alloc = nvkm_bar_alloc; bar->base.alloc = nvkm_bar_alloc;
priv->base.kmap = nv50_bar_kmap; bar->base.kmap = nv50_bar_kmap;
priv->base.umap = nv50_bar_umap; bar->base.umap = nv50_bar_umap;
priv->base.unmap = nv50_bar_unmap; bar->base.unmap = nv50_bar_unmap;
if (device->chipset == 0x50) if (device->chipset == 0x50)
priv->base.flush = nv50_bar_flush; bar->base.flush = nv50_bar_flush;
else else
priv->base.flush = g84_bar_flush; bar->base.flush = g84_bar_flush;
spin_lock_init(&priv->lock); spin_lock_init(&bar->lock);
return 0; return 0;
} }
static void static void
nv50_bar_dtor(struct nvkm_object *object) nv50_bar_dtor(struct nvkm_object *object)
{ {
struct nv50_bar_priv *priv = (void *)object; struct nv50_bar *bar = (void *)object;
nvkm_gpuobj_ref(NULL, &priv->bar1); nvkm_gpuobj_ref(NULL, &bar->bar1);
nvkm_vm_ref(NULL, &priv->bar1_vm, priv->pgd); nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);
nvkm_gpuobj_ref(NULL, &priv->bar3); nvkm_gpuobj_ref(NULL, &bar->bar3);
if (priv->bar3_vm) { if (bar->bar3_vm) {
nvkm_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]); nvkm_gpuobj_ref(NULL, &bar->bar3_vm->pgt[0].obj[0]);
nvkm_vm_ref(NULL, &priv->bar3_vm, priv->pgd); nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);
} }
nvkm_gpuobj_ref(NULL, &priv->pgd); nvkm_gpuobj_ref(NULL, &bar->pgd);
nvkm_gpuobj_ref(NULL, &priv->pad); nvkm_gpuobj_ref(NULL, &bar->pad);
nvkm_gpuobj_ref(NULL, &priv->mem); nvkm_gpuobj_ref(NULL, &bar->mem);
nvkm_bar_destroy(&priv->base); nvkm_bar_destroy(&bar->base);
} }
static int static int
nv50_bar_init(struct nvkm_object *object) nv50_bar_init(struct nvkm_object *object)
{ {
struct nv50_bar_priv *priv = (void *)object; struct nv50_bar *bar = (void *)object;
int ret, i; int ret, i;
ret = nvkm_bar_init(&priv->base); ret = nvkm_bar_init(&bar->base);
if (ret) if (ret)
return ret; return ret;
nv_mask(priv, 0x000200, 0x00000100, 0x00000000); nv_mask(bar, 0x000200, 0x00000100, 0x00000000);
nv_mask(priv, 0x000200, 0x00000100, 0x00000100); nv_mask(bar, 0x000200, 0x00000100, 0x00000100);
nv_wr32(priv, 0x100c80, 0x00060001); nv_wr32(bar, 0x100c80, 0x00060001);
if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) { if (!nv_wait(bar, 0x100c80, 0x00000001, 0x00000000)) {
nv_error(priv, "vm flush timeout\n"); nv_error(bar, "vm flush timeout\n");
return -EBUSY; return -EBUSY;
} }
nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12); nv_wr32(bar, 0x001704, 0x00000000 | bar->mem->addr >> 12);
nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12); nv_wr32(bar, 0x001704, 0x40000000 | bar->mem->addr >> 12);
nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4); nv_wr32(bar, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4); nv_wr32(bar, 0x00170c, 0x80000000 | bar->bar3->node->offset >> 4);
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
nv_wr32(priv, 0x001900 + (i * 4), 0x00000000); nv_wr32(bar, 0x001900 + (i * 4), 0x00000000);
return 0; return 0;
} }
static int static int
nv50_bar_fini(struct nvkm_object *object, bool suspend) nv50_bar_fini(struct nvkm_object *object, bool suspend)
{ {
struct nv50_bar_priv *priv = (void *)object; struct nv50_bar *bar = (void *)object;
return nvkm_bar_fini(&priv->base, suspend); return nvkm_bar_fini(&bar->base, suspend);
} }
struct nvkm_oclass struct nvkm_oclass
......
drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
View file @ 5b0c189f
...@@ -5,9 +5,9 @@ ...@@ -5,9 +5,9 @@
#define nvkm_bar_create(p,e,o,d) \ #define nvkm_bar_create(p,e,o,d) \
nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d) nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_bar_init(p) \ #define nvkm_bar_init(p) \
nvkm_subdev_init(&(p)->base) nvkm_subdev_init(&(p)->subdev)
#define nvkm_bar_fini(p,s) \ #define nvkm_bar_fini(p,s) \
nvkm_subdev_fini(&(p)->base, (s)) nvkm_subdev_fini(&(p)->subdev, (s))
int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *, int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **); struct nvkm_oclass *, int, void **);
......
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