Commit 5b2acf38 authored by Shawn Guo's avatar Shawn Guo

ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidation

The recent suspend/resume and reset testing on imx6q discovers that
not only D-Cache but also I-Cache has random data and validity when
the core comes out of a power recycle.

This patch adds I-Cache invalidation into v7_invalidate_l1 to make
sure both D-Cache and I-Cache invalidated on power-up.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 5f0a6e2d
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
*/ */
ENTRY(v7_invalidate_l1) ENTRY(v7_invalidate_l1)
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 2, r0, c0, c0, 0 mcr p15, 2, r0, c0, c0, 0
mrc p15, 1, r0, c0, c0, 0 mrc p15, 1, r0, c0, c0, 0
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment