Commit 5b5fa355 authored by Sujith's avatar Sujith Committed by John W. Linville

ath9k_hw: add GPIO setup code for AR9271

Assign the proper number of GPIO pins for AR9271.
Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarVasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 70807e99
...@@ -3229,7 +3229,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) ...@@ -3229,7 +3229,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
else else
pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
if (AR_SREV_9285_10_OR_LATER(ah)) if (AR_SREV_9271(ah))
pCap->num_gpio_pins = AR9271_NUM_GPIO;
else if (AR_SREV_9285_10_OR_LATER(ah))
pCap->num_gpio_pins = AR9285_NUM_GPIO; pCap->num_gpio_pins = AR9285_NUM_GPIO;
else if (AR_SREV_9280_10_OR_LATER(ah)) else if (AR_SREV_9280_10_OR_LATER(ah))
pCap->num_gpio_pins = AR928X_NUM_GPIO; pCap->num_gpio_pins = AR928X_NUM_GPIO;
...@@ -3465,7 +3467,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) ...@@ -3465,7 +3467,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
if (gpio >= ah->caps.num_gpio_pins) if (gpio >= ah->caps.num_gpio_pins)
return 0xffffffff; return 0xffffffff;
if (AR_SREV_9287_10_OR_LATER(ah)) if (AR_SREV_9271(ah))
return MS_REG_READ(AR9271, gpio) != 0;
else if (AR_SREV_9287_10_OR_LATER(ah))
return MS_REG_READ(AR9287, gpio) != 0; return MS_REG_READ(AR9287, gpio) != 0;
else if (AR_SREV_9285_10_OR_LATER(ah)) else if (AR_SREV_9285_10_OR_LATER(ah))
return MS_REG_READ(AR9285, gpio) != 0; return MS_REG_READ(AR9285, gpio) != 0;
...@@ -3494,6 +3498,9 @@ EXPORT_SYMBOL(ath9k_hw_cfg_output); ...@@ -3494,6 +3498,9 @@ EXPORT_SYMBOL(ath9k_hw_cfg_output);
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
{ {
if (AR_SREV_9271(ah))
val = ~val;
REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
AR_GPIO_BIT(gpio)); AR_GPIO_BIT(gpio));
} }
......
...@@ -940,6 +940,7 @@ enum { ...@@ -940,6 +940,7 @@ enum {
#define AR928X_NUM_GPIO 10 #define AR928X_NUM_GPIO 10
#define AR9285_NUM_GPIO 12 #define AR9285_NUM_GPIO 12
#define AR9287_NUM_GPIO 11 #define AR9287_NUM_GPIO 11
#define AR9271_NUM_GPIO 16
#define AR_GPIO_IN_OUT 0x4048 #define AR_GPIO_IN_OUT 0x4048
#define AR_GPIO_IN_VAL 0x0FFFC000 #define AR_GPIO_IN_VAL 0x0FFFC000
...@@ -950,6 +951,8 @@ enum { ...@@ -950,6 +951,8 @@ enum {
#define AR9285_GPIO_IN_VAL_S 12 #define AR9285_GPIO_IN_VAL_S 12
#define AR9287_GPIO_IN_VAL 0x003FF800 #define AR9287_GPIO_IN_VAL 0x003FF800
#define AR9287_GPIO_IN_VAL_S 11 #define AR9287_GPIO_IN_VAL_S 11
#define AR9271_GPIO_IN_VAL 0xFFFF0000
#define AR9271_GPIO_IN_VAL_S 16
#define AR_GPIO_OE_OUT 0x404c #define AR_GPIO_OE_OUT 0x404c
#define AR_GPIO_OE_OUT_DRV 0x3 #define AR_GPIO_OE_OUT_DRV 0x3
......
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