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Commit 5c152912 authored by Mike Rapoport's avatar Mike Rapoport Committed by Bartlomiej Zolnierkiewicz
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fbdev: remove mbx framebuffer driver 

The only in-tree user for mbx driver for Intel 2700G graphics chip was
cm-x270 platform. Since this platform was removed by the commit
9d323914 ("ARM: pxa: remove Compulab pxa2xx boards") there is no
point to keep the obsolete framebuffer driver.
Signed-off-by: default avatarMike Rapoport <rppt@linux.ibm.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200830115524.431278-1-rppt@kernel.org
parent 28657c30
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Documentation/userspace-api/ioctl/ioctl-number.rst
View file @ 5c152912
......@@ -356,8 +356,6 @@ Code Seq# Include File Comments
0xEC 00-01 drivers/platform/chrome/cros_ec_dev.h ChromeOS EC driver
0xF3 00-3F drivers/usb/misc/sisusbvga/sisusb.h sisfb (in development)
<mailto:thomas@winischhofer.net>
0xF4 00-1F video/mbxfb.h mbxfb
<mailto:raph@8d.com>
0xF6 all LTTng Linux Trace Toolkit Next Generation
<mailto:mathieu.desnoyers@efficios.com>
0xFD all linux/dm-ioctl.h
......
drivers/video/fbdev/Kconfig
View file @ 5c152912
......@@ -1775,25 +1775,6 @@ config PXA3XX_GCU
If you compile this as a module, it will be called pxa3xx_gcu.
config FB_MBX
tristate "2700G LCD framebuffer support"
depends on FB && ARCH_PXA
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
help
Framebuffer driver for the Intel 2700G (Marathon) Graphics
Accelerator
config FB_MBX_DEBUG
bool "Enable debugging info via debugfs"
depends on FB_MBX && DEBUG_FS
help
Enable this if you want debugging information using the debug
filesystem (debugfs)
If unsure, say N.
config FB_FSL_DIU
tristate "Freescale DIU framebuffer support"
depends on FB && FSL_SOC
......
drivers/video/fbdev/Makefile
View file @ 5c152912
......@@ -31,7 +31,6 @@ obj-$(CONFIG_FB_VIA) += via/
obj-$(CONFIG_FB_KYRO) += kyro/
obj-$(CONFIG_FB_SAVAGE) += savage/
obj-$(CONFIG_FB_GEODE) += geode/
obj-$(CONFIG_FB_MBX) += mbx/
obj-$(CONFIG_FB_NEOMAGIC) += neofb.o
obj-$(CONFIG_FB_3DFX) += tdfxfb.o
obj-$(CONFIG_FB_CONTROL) += controlfb.o
......
drivers/video/fbdev/mbx/Makefile deleted 100644 → 0
View file @ 28657c30
# SPDX-License-Identifier: GPL-2.0-only
# Makefile for the 2700G controller driver.
obj-y += mbxfb.o
drivers/video/fbdev/mbx/mbxdebugfs.c deleted 100644 → 0
View file @ 28657c30
// SPDX-License-Identifier: GPL-2.0
#include <linux/debugfs.h>
#include <linux/slab.h>
#define BIG_BUFFER_SIZE (1024)
static char big_buffer[BIG_BUFFER_SIZE];
struct mbxfb_debugfs_data {
struct dentry *dir;
struct dentry *sysconf;
struct dentry *clock;
struct dentry *display;
struct dentry *gsctl;
struct dentry *sdram;
struct dentry *misc;
};
static ssize_t write_file_dummy(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
return count;
}
static ssize_t sysconf_read_file(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
char * s = big_buffer;
s += sprintf(s, "SYSCFG = %08x\n", readl(SYSCFG));
s += sprintf(s, "PFBASE = %08x\n", readl(PFBASE));
s += sprintf(s, "PFCEIL = %08x\n", readl(PFCEIL));
s += sprintf(s, "POLLFLAG = %08x\n", readl(POLLFLAG));
s += sprintf(s, "SYSRST = %08x\n", readl(SYSRST));
return simple_read_from_buffer(userbuf, count, ppos,
big_buffer, s-big_buffer);
}
static ssize_t gsctl_read_file(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
char * s = big_buffer;
s += sprintf(s, "GSCTRL = %08x\n", readl(GSCTRL));
s += sprintf(s, "VSCTRL = %08x\n", readl(VSCTRL));
s += sprintf(s, "GBBASE = %08x\n", readl(GBBASE));
s += sprintf(s, "VBBASE = %08x\n", readl(VBBASE));
s += sprintf(s, "GDRCTRL = %08x\n", readl(GDRCTRL));
s += sprintf(s, "VCMSK = %08x\n", readl(VCMSK));
s += sprintf(s, "GSCADR = %08x\n", readl(GSCADR));
s += sprintf(s, "VSCADR = %08x\n", readl(VSCADR));
s += sprintf(s, "VUBASE = %08x\n", readl(VUBASE));
s += sprintf(s, "VVBASE = %08x\n", readl(VVBASE));
s += sprintf(s, "GSADR = %08x\n", readl(GSADR));
s += sprintf(s, "VSADR = %08x\n", readl(VSADR));
s += sprintf(s, "HCCTRL = %08x\n", readl(HCCTRL));
s += sprintf(s, "HCSIZE = %08x\n", readl(HCSIZE));
s += sprintf(s, "HCPOS = %08x\n", readl(HCPOS));
s += sprintf(s, "HCBADR = %08x\n", readl(HCBADR));
s += sprintf(s, "HCCKMSK = %08x\n", readl(HCCKMSK));
s += sprintf(s, "GPLUT = %08x\n", readl(GPLUT));
return simple_read_from_buffer(userbuf, count, ppos,
big_buffer, s-big_buffer);
}
static ssize_t display_read_file(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
char * s = big_buffer;
s += sprintf(s, "DSCTRL = %08x\n", readl(DSCTRL));
s += sprintf(s, "DHT01 = %08x\n", readl(DHT01));
s += sprintf(s, "DHT02 = %08x\n", readl(DHT02));
s += sprintf(s, "DHT03 = %08x\n", readl(DHT03));
s += sprintf(s, "DVT01 = %08x\n", readl(DVT01));
s += sprintf(s, "DVT02 = %08x\n", readl(DVT02));
s += sprintf(s, "DVT03 = %08x\n", readl(DVT03));
s += sprintf(s, "DBCOL = %08x\n", readl(DBCOL));
s += sprintf(s, "BGCOLOR = %08x\n", readl(BGCOLOR));
s += sprintf(s, "DINTRS = %08x\n", readl(DINTRS));
s += sprintf(s, "DINTRE = %08x\n", readl(DINTRE));
s += sprintf(s, "DINTRCNT = %08x\n", readl(DINTRCNT));
s += sprintf(s, "DSIG = %08x\n", readl(DSIG));
s += sprintf(s, "DMCTRL = %08x\n", readl(DMCTRL));
s += sprintf(s, "CLIPCTRL = %08x\n", readl(CLIPCTRL));
s += sprintf(s, "SPOCTRL = %08x\n", readl(SPOCTRL));
s += sprintf(s, "SVCTRL = %08x\n", readl(SVCTRL));
s += sprintf(s, "DLSTS = %08x\n", readl(DLSTS));
s += sprintf(s, "DLLCTRL = %08x\n", readl(DLLCTRL));
s += sprintf(s, "DVLNUM = %08x\n", readl(DVLNUM));
s += sprintf(s, "DUCTRL = %08x\n", readl(DUCTRL));
s += sprintf(s, "DVECTRL = %08x\n", readl(DVECTRL));
s += sprintf(s, "DHDET = %08x\n", readl(DHDET));
s += sprintf(s, "DVDET = %08x\n", readl(DVDET));
s += sprintf(s, "DODMSK = %08x\n", readl(DODMSK));
s += sprintf(s, "CSC01 = %08x\n", readl(CSC01));
s += sprintf(s, "CSC02 = %08x\n", readl(CSC02));
s += sprintf(s, "CSC03 = %08x\n", readl(CSC03));
s += sprintf(s, "CSC04 = %08x\n", readl(CSC04));
s += sprintf(s, "CSC05 = %08x\n", readl(CSC05));
return simple_read_from_buffer(userbuf, count, ppos,
big_buffer, s-big_buffer);
}
static ssize_t clock_read_file(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
char * s = big_buffer;
s += sprintf(s, "SYSCLKSRC = %08x\n", readl(SYSCLKSRC));
s += sprintf(s, "PIXCLKSRC = %08x\n", readl(PIXCLKSRC));
s += sprintf(s, "CLKSLEEP = %08x\n", readl(CLKSLEEP));
s += sprintf(s, "COREPLL = %08x\n", readl(COREPLL));
s += sprintf(s, "DISPPLL = %08x\n", readl(DISPPLL));
s += sprintf(s, "PLLSTAT = %08x\n", readl(PLLSTAT));
s += sprintf(s, "VOVRCLK = %08x\n", readl(VOVRCLK));
s += sprintf(s, "PIXCLK = %08x\n", readl(PIXCLK));
s += sprintf(s, "MEMCLK = %08x\n", readl(MEMCLK));
s += sprintf(s, "M24CLK = %08x\n", readl(M24CLK));
s += sprintf(s, "MBXCLK = %08x\n", readl(MBXCLK));
s += sprintf(s, "SDCLK = %08x\n", readl(SDCLK));
s += sprintf(s, "PIXCLKDIV = %08x\n", readl(PIXCLKDIV));
return simple_read_from_buffer(userbuf, count, ppos,
big_buffer, s-big_buffer);
}
static ssize_t sdram_read_file(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
char * s = big_buffer;
s += sprintf(s, "LMRST = %08x\n", readl(LMRST));
s += sprintf(s, "LMCFG = %08x\n", readl(LMCFG));
s += sprintf(s, "LMPWR = %08x\n", readl(LMPWR));
s += sprintf(s, "LMPWRSTAT = %08x\n", readl(LMPWRSTAT));
s += sprintf(s, "LMCEMR = %08x\n", readl(LMCEMR));
s += sprintf(s, "LMTYPE = %08x\n", readl(LMTYPE));
s += sprintf(s, "LMTIM = %08x\n", readl(LMTIM));
s += sprintf(s, "LMREFRESH = %08x\n", readl(LMREFRESH));
s += sprintf(s, "LMPROTMIN = %08x\n", readl(LMPROTMIN));
s += sprintf(s, "LMPROTMAX = %08x\n", readl(LMPROTMAX));
s += sprintf(s, "LMPROTCFG = %08x\n", readl(LMPROTCFG));
s += sprintf(s, "LMPROTERR = %08x\n", readl(LMPROTERR));
return simple_read_from_buffer(userbuf, count, ppos,
big_buffer, s-big_buffer);
}
static ssize_t misc_read_file(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
char * s = big_buffer;
s += sprintf(s, "LCD_CONFIG = %08x\n", readl(LCD_CONFIG));
s += sprintf(s, "ODFBPWR = %08x\n", readl(ODFBPWR));
s += sprintf(s, "ODFBSTAT = %08x\n", readl(ODFBSTAT));
s += sprintf(s, "ID = %08x\n", readl(ID));
return simple_read_from_buffer(userbuf, count, ppos,
big_buffer, s-big_buffer);
}
static const struct file_operations sysconf_fops = {
.read = sysconf_read_file,
.write = write_file_dummy,
.open = simple_open,
.llseek = default_llseek,
};
static const struct file_operations clock_fops = {
.read = clock_read_file,
.write = write_file_dummy,
.open = simple_open,
.llseek = default_llseek,
};
static const struct file_operations display_fops = {
.read = display_read_file,
.write = write_file_dummy,
.open = simple_open,
.llseek = default_llseek,
};
static const struct file_operations gsctl_fops = {
.read = gsctl_read_file,
.write = write_file_dummy,
.open = simple_open,
.llseek = default_llseek,
};
static const struct file_operations sdram_fops = {
.read = sdram_read_file,
.write = write_file_dummy,
.open = simple_open,
.llseek = default_llseek,
};
static const struct file_operations misc_fops = {
.read = misc_read_file,
.write = write_file_dummy,
.open = simple_open,
.llseek = default_llseek,
};
static void mbxfb_debugfs_init(struct fb_info *fbi)
{
struct mbxfb_info *mfbi = fbi->par;
struct dentry *dir;
dir = debugfs_create_dir("mbxfb", NULL);
mfbi->debugfs_dir = dir;
debugfs_create_file("sysconf", 0444, dir, fbi, &sysconf_fops);
debugfs_create_file("clock", 0444, dir, fbi, &clock_fops);
debugfs_create_file("display", 0444, dir, fbi, &display_fops);
debugfs_create_file("gsctl", 0444, dir, fbi, &gsctl_fops);
debugfs_create_file("sdram", 0444, dir, fbi, &sdram_fops);
debugfs_create_file("misc", 0444, dir, fbi, &misc_fops);
}
static void mbxfb_debugfs_remove(struct fb_info *fbi)
{
struct mbxfb_info *mfbi = fbi->par;
debugfs_remove_recursive(mfbi->debugfs_dir);
}
drivers/video/fbdev/mbx/mbxfb.c deleted 100644 → 0
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drivers/video/fbdev/mbx/reg_bits.h deleted 100644 → 0
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drivers/video/fbdev/mbx/regs.h deleted 100644 → 0
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __REGS_2700G_
#define __REGS_2700G_
/* extern unsigned long virt_base_2700; */
/* #define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700)) */
#define __REG_2700G(x) ((x)+virt_base_2700)
/* System Configuration Registers (0x0000_0000 0x0000_0010) */
#define SYSCFG __REG_2700G(0x00000000)
#define PFBASE __REG_2700G(0x00000004)
#define PFCEIL __REG_2700G(0x00000008)
#define POLLFLAG __REG_2700G(0x0000000c)
#define SYSRST __REG_2700G(0x00000010)
/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
#define NINTPW __REG_2700G(0x00000014)
#define MINTENABLE __REG_2700G(0x00000018)
#define MINTSTAT __REG_2700G(0x0000001c)
#define SINTENABLE __REG_2700G(0x00000020)
#define SINTSTAT __REG_2700G(0x00000024)
#define SINTCLR __REG_2700G(0x00000028)
/* Clock Control Registers (0x0000_002C 0x0000_005F) */
#define SYSCLKSRC __REG_2700G(0x0000002c)
#define PIXCLKSRC __REG_2700G(0x00000030)
#define CLKSLEEP __REG_2700G(0x00000034)
#define COREPLL __REG_2700G(0x00000038)
#define DISPPLL __REG_2700G(0x0000003c)
#define PLLSTAT __REG_2700G(0x00000040)
#define VOVRCLK __REG_2700G(0x00000044)
#define PIXCLK __REG_2700G(0x00000048)
#define MEMCLK __REG_2700G(0x0000004c)
#define M24CLK __REG_2700G(0x00000050)
#define MBXCLK __REG_2700G(0x00000054)
#define SDCLK __REG_2700G(0x00000058)
#define PIXCLKDIV __REG_2700G(0x0000005c)
/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
#define LCD_CONFIG __REG_2700G(0x00000060)
/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
#define ODFBPWR __REG_2700G(0x00000064)
#define ODFBSTAT __REG_2700G(0x00000068)
/* GPIO Registers (0x0000_006C 0x0000_007F) */
#define GPIOCGF __REG_2700G(0x0000006c)
#define GPIOHI __REG_2700G(0x00000070)
#define GPIOLO __REG_2700G(0x00000074)
#define GPIOSTAT __REG_2700G(0x00000078)
/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
#define PWMRST __REG_2700G(0x00000200)
#define PWMCFG __REG_2700G(0x00000204)
#define PWM0DIV __REG_2700G(0x00000210)
#define PWM0DUTY __REG_2700G(0x00000214)
#define PWM0PER __REG_2700G(0x00000218)
#define PWM1DIV __REG_2700G(0x00000220)
#define PWM1DUTY __REG_2700G(0x00000224)
#define PWM1PER __REG_2700G(0x00000228)
/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
#define ID __REG_2700G(0x00000FF0)
/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
#define LMRST __REG_2700G(0x00001000)
#define LMCFG __REG_2700G(0x00001004)
#define LMPWR __REG_2700G(0x00001008)
#define LMPWRSTAT __REG_2700G(0x0000100c)
#define LMCEMR __REG_2700G(0x00001010)
#define LMTYPE __REG_2700G(0x00001014)
#define LMTIM __REG_2700G(0x00001018)
#define LMREFRESH __REG_2700G(0x0000101c)
#define LMPROTMIN __REG_2700G(0x00001020)
#define LMPROTMAX __REG_2700G(0x00001024)
#define LMPROTCFG __REG_2700G(0x00001028)
#define LMPROTERR __REG_2700G(0x0000102c)
/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
#define GSCTRL __REG_2700G(0x00002000)
#define VSCTRL __REG_2700G(0x00002004)
#define GBBASE __REG_2700G(0x00002020)
#define VBBASE __REG_2700G(0x00002024)
#define GDRCTRL __REG_2700G(0x00002040)
#define VCMSK __REG_2700G(0x00002044)
#define GSCADR __REG_2700G(0x00002060)
#define VSCADR __REG_2700G(0x00002064)
#define VUBASE __REG_2700G(0x00002084)
#define VVBASE __REG_2700G(0x000020a4)
#define GSADR __REG_2700G(0x000020c0)
#define VSADR __REG_2700G(0x000020c4)
#define HCCTRL __REG_2700G(0x00002100)
#define HCSIZE __REG_2700G(0x00002110)
#define HCPOS __REG_2700G(0x00002120)
#define HCBADR __REG_2700G(0x00002130)
#define HCCKMSK __REG_2700G(0x00002140)
#define GPLUT __REG_2700G(0x00002150)
#define DSCTRL __REG_2700G(0x00002154)
#define DHT01 __REG_2700G(0x00002158)
#define DHT02 __REG_2700G(0x0000215c)
#define DHT03 __REG_2700G(0x00002160)
#define DVT01 __REG_2700G(0x00002164)
#define DVT02 __REG_2700G(0x00002168)
#define DVT03 __REG_2700G(0x0000216c)
#define DBCOL __REG_2700G(0x00002170)
#define BGCOLOR __REG_2700G(0x00002174)
#define DINTRS __REG_2700G(0x00002178)
#define DINTRE __REG_2700G(0x0000217c)
#define DINTRCNT __REG_2700G(0x00002180)
#define DSIG __REG_2700G(0x00002184)
#define DMCTRL __REG_2700G(0x00002188)
#define CLIPCTRL __REG_2700G(0x0000218c)
#define SPOCTRL __REG_2700G(0x00002190)
#define SVCTRL __REG_2700G(0x00002194)
/* 0x0000_2198 */
/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
#define VSCOEFF0 __REG_2700G(0x00002198)
#define VSCOEFF1 __REG_2700G(0x0000219c)
#define VSCOEFF2 __REG_2700G(0x000021a0)
#define VSCOEFF3 __REG_2700G(0x000021a4)
#define VSCOEFF4 __REG_2700G(0x000021a8)
#define SHCTRL __REG_2700G(0x000021b0)
/* 0x0000_21B4 */
/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
#define HSCOEFF0 __REG_2700G(0x000021b4)
#define HSCOEFF1 __REG_2700G(0x000021b8)
#define HSCOEFF2 __REG_2700G(0x000021bc)
#define HSCOEFF3 __REG_2700G(0x000021c0)
#define HSCOEFF4 __REG_2700G(0x000021c4)
#define HSCOEFF5 __REG_2700G(0x000021c8)
#define HSCOEFF6 __REG_2700G(0x000021cc)
#define HSCOEFF7 __REG_2700G(0x000021d0)
#define HSCOEFF8 __REG_2700G(0x000021d4)
#define SSSIZE __REG_2700G(0x000021D8)
/* 0x0000_2200 */
/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
#define VIDGAM0 __REG_2700G(0x00002200)
#define VIDGAM1 __REG_2700G(0x00002204)
#define VIDGAM2 __REG_2700G(0x00002208)
#define VIDGAM3 __REG_2700G(0x0000220c)
#define VIDGAM4 __REG_2700G(0x00002210)
#define VIDGAM5 __REG_2700G(0x00002214)
#define VIDGAM6 __REG_2700G(0x00002218)
#define VIDGAM7 __REG_2700G(0x0000221c)
#define VIDGAM8 __REG_2700G(0x00002220)
#define VIDGAM9 __REG_2700G(0x00002224)
#define VIDGAM10 __REG_2700G(0x00002228)
#define VIDGAM11 __REG_2700G(0x0000222c)
#define VIDGAM12 __REG_2700G(0x00002230)
#define VIDGAM13 __REG_2700G(0x00002234)
#define VIDGAM14 __REG_2700G(0x00002238)
#define VIDGAM15 __REG_2700G(0x0000223c)
#define VIDGAM16 __REG_2700G(0x00002240)
/* 0x0000_2250 */
/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
#define GFXGAM0 __REG_2700G(0x00002250)
#define GFXGAM1 __REG_2700G(0x00002254)
#define GFXGAM2 __REG_2700G(0x00002258)
#define GFXGAM3 __REG_2700G(0x0000225c)
#define GFXGAM4 __REG_2700G(0x00002260)
#define GFXGAM5 __REG_2700G(0x00002264)
#define GFXGAM6 __REG_2700G(0x00002268)
#define GFXGAM7 __REG_2700G(0x0000226c)
#define GFXGAM8 __REG_2700G(0x00002270)
#define GFXGAM9 __REG_2700G(0x00002274)
#define GFXGAM10 __REG_2700G(0x00002278)
#define GFXGAM11 __REG_2700G(0x0000227c)
#define GFXGAM12 __REG_2700G(0x00002280)
#define GFXGAM13 __REG_2700G(0x00002284)
#define GFXGAM14 __REG_2700G(0x00002288)
#define GFXGAM15 __REG_2700G(0x0000228c)
#define GFXGAM16 __REG_2700G(0x00002290)
#define DLSTS __REG_2700G(0x00002300)
#define DLLCTRL __REG_2700G(0x00002304)
#define DVLNUM __REG_2700G(0x00002308)
#define DUCTRL __REG_2700G(0x0000230c)
#define DVECTRL __REG_2700G(0x00002310)
#define DHDET __REG_2700G(0x00002314)
#define DVDET __REG_2700G(0x00002318)
#define DODMSK __REG_2700G(0x0000231c)
#define CSC01 __REG_2700G(0x00002330)
#define CSC02 __REG_2700G(0x00002334)
#define CSC03 __REG_2700G(0x00002338)
#define CSC04 __REG_2700G(0x0000233c)
#define CSC05 __REG_2700G(0x00002340)
#define FB_MEMORY_START __REG_2700G(0x00060000)
#endif /* __REGS_2700G_ */
include/video/mbxfb.h deleted 100644 → 0
View file @ 28657c30
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __MBX_FB_H
#define __MBX_FB_H
#include <asm/ioctl.h>
#include <asm/types.h>
struct mbxfb_val {
unsigned int defval;
unsigned int min;
unsigned int max;
};
struct fb_info;
struct mbxfb_platform_data {
/* Screen info */
struct mbxfb_val xres;
struct mbxfb_val yres;
struct mbxfb_val bpp;
/* Memory info */
unsigned long memsize; /* if 0 use ODFB? */
unsigned long timings1;
unsigned long timings2;
unsigned long timings3;
int (*probe)(struct fb_info *fb);
int (*remove)(struct fb_info *fb);
};
/* planar */
#define MBXFB_FMT_YUV16 0
#define MBXFB_FMT_YUV12 1
/* packed */
#define MBXFB_FMT_UY0VY1 2
#define MBXFB_FMT_VY0UY1 3
#define MBXFB_FMT_Y0UY1V 4
#define MBXFB_FMT_Y0VY1U 5
struct mbxfb_overlaySetup {
__u32 enable;
__u32 x, y;
__u32 width, height;
__u32 fmt;
__u32 mem_offset;
__u32 scaled_width;
__u32 scaled_height;
/* Filled by the driver */
__u32 U_offset;
__u32 V_offset;
__u16 Y_stride;
__u16 UV_stride;
};
#define MBXFB_ALPHABLEND_NONE 0
#define MBXFB_ALPHABLEND_GLOBAL 1
#define MBXFB_ALPHABLEND_PIXEL 2
#define MBXFB_COLORKEY_DISABLED 0
#define MBXFB_COLORKEY_PREVIOUS 1
#define MBXFB_COLORKEY_CURRENT 2
struct mbxfb_alphaCtl {
__u8 overlay_blend_mode;
__u8 overlay_colorkey_mode;
__u8 overlay_global_alpha;
__u32 overlay_colorkey;
__u32 overlay_colorkey_mask;
__u8 graphics_blend_mode;
__u8 graphics_colorkey_mode;
__u8 graphics_global_alpha;
__u32 graphics_colorkey;
__u32 graphics_colorkey_mask;
};
#define MBXFB_PLANE_GRAPHICS 0
#define MBXFB_PLANE_VIDEO 1
struct mbxfb_planeorder {
__u8 bottom;
__u8 top;
};
struct mbxfb_reg {
__u32 addr; /* offset from 0x03fe 0000 */
__u32 val; /* value */
__u32 mask; /* which bits to touch (for write) */
};
#define MBXFB_IOCX_OVERLAY _IOWR(0xF4, 0x00,struct mbxfb_overlaySetup)
#define MBXFB_IOCG_ALPHA _IOR(0xF4, 0x01,struct mbxfb_alphaCtl)
#define MBXFB_IOCS_ALPHA _IOW(0xF4, 0x02,struct mbxfb_alphaCtl)
#define MBXFB_IOCS_PLANEORDER _IOR(0xF4, 0x03,struct mbxfb_planeorder)
#define MBXFB_IOCS_REG _IOW(0xF4, 0x04,struct mbxfb_reg)
#define MBXFB_IOCX_REG _IOWR(0xF4, 0x05,struct mbxfb_reg)
#endif /* __MBX_FB_H */
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