Commit 5c49985c authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm

Pull ARM fixes from Russell King.

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
  ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
  ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
  ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
  ARM: 7611/1: VIC: fix bug in VIC irqdomain code
  ARM: 7610/1: versatile: bump IRQ numbers
  ARM: 7609/1: disable errata work-arounds which access secure registers
  ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
parents 57a0c1e2 8a3a180d
...@@ -1229,6 +1229,7 @@ config ARM_ERRATA_430973 ...@@ -1229,6 +1229,7 @@ config ARM_ERRATA_430973
config ARM_ERRATA_458693 config ARM_ERRATA_458693
bool "ARM errata: Processor deadlock when a false hazard is created" bool "ARM errata: Processor deadlock when a false hazard is created"
depends on CPU_V7 depends on CPU_V7
depends on !ARCH_MULTIPLATFORM
help help
This option enables the workaround for the 458693 Cortex-A8 (r2p0) This option enables the workaround for the 458693 Cortex-A8 (r2p0)
erratum. For very specific sequences of memory operations, it is erratum. For very specific sequences of memory operations, it is
...@@ -1242,6 +1243,7 @@ config ARM_ERRATA_458693 ...@@ -1242,6 +1243,7 @@ config ARM_ERRATA_458693
config ARM_ERRATA_460075 config ARM_ERRATA_460075
bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
depends on CPU_V7 depends on CPU_V7
depends on !ARCH_MULTIPLATFORM
help help
This option enables the workaround for the 460075 Cortex-A8 (r2p0) This option enables the workaround for the 460075 Cortex-A8 (r2p0)
erratum. Any asynchronous access to the L2 cache may encounter a erratum. Any asynchronous access to the L2 cache may encounter a
...@@ -1254,6 +1256,7 @@ config ARM_ERRATA_460075 ...@@ -1254,6 +1256,7 @@ config ARM_ERRATA_460075
config ARM_ERRATA_742230 config ARM_ERRATA_742230
bool "ARM errata: DMB operation may be faulty" bool "ARM errata: DMB operation may be faulty"
depends on CPU_V7 && SMP depends on CPU_V7 && SMP
depends on !ARCH_MULTIPLATFORM
help help
This option enables the workaround for the 742230 Cortex-A9 This option enables the workaround for the 742230 Cortex-A9
(r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
...@@ -1266,6 +1269,7 @@ config ARM_ERRATA_742230 ...@@ -1266,6 +1269,7 @@ config ARM_ERRATA_742230
config ARM_ERRATA_742231 config ARM_ERRATA_742231
bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
depends on CPU_V7 && SMP depends on CPU_V7 && SMP
depends on !ARCH_MULTIPLATFORM
help help
This option enables the workaround for the 742231 Cortex-A9 This option enables the workaround for the 742231 Cortex-A9
(r2p0..r2p2) erratum. Under certain conditions, specific to the (r2p0..r2p2) erratum. Under certain conditions, specific to the
...@@ -1316,6 +1320,7 @@ config PL310_ERRATA_727915 ...@@ -1316,6 +1320,7 @@ config PL310_ERRATA_727915
config ARM_ERRATA_743622 config ARM_ERRATA_743622
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
depends on CPU_V7 depends on CPU_V7
depends on !ARCH_MULTIPLATFORM
help help
This option enables the workaround for the 743622 Cortex-A9 This option enables the workaround for the 743622 Cortex-A9
(r2p*) erratum. Under very rare conditions, a faulty (r2p*) erratum. Under very rare conditions, a faulty
...@@ -1329,6 +1334,7 @@ config ARM_ERRATA_743622 ...@@ -1329,6 +1334,7 @@ config ARM_ERRATA_743622
config ARM_ERRATA_751472 config ARM_ERRATA_751472
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
depends on CPU_V7 depends on CPU_V7
depends on !ARCH_MULTIPLATFORM
help help
This option enables the workaround for the 751472 Cortex-A9 (prior This option enables the workaround for the 751472 Cortex-A9 (prior
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
......
...@@ -206,6 +206,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq, ...@@ -206,6 +206,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
struct device_node *node) struct device_node *node)
{ {
struct vic_device *v; struct vic_device *v;
int i;
if (vic_id >= ARRAY_SIZE(vic_devices)) { if (vic_id >= ARRAY_SIZE(vic_devices)) {
printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
...@@ -220,6 +221,10 @@ static void __init vic_register(void __iomem *base, unsigned int irq, ...@@ -220,6 +221,10 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
vic_id++; vic_id++;
v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
&vic_irqdomain_ops, v); &vic_irqdomain_ops, v);
/* create an IRQ mapping for each valid IRQ */
for (i = 0; i < fls(valid_sources); i++)
if (valid_sources & (1 << i))
irq_create_mapping(v->domain, i);
} }
static void vic_ack_irq(struct irq_data *d) static void vic_ack_irq(struct irq_data *d)
...@@ -416,9 +421,9 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent) ...@@ -416,9 +421,9 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
return -EIO; return -EIO;
/* /*
* Passing -1 as first IRQ makes the simple domain allocate descriptors * Passing 0 as first IRQ makes the simple domain allocate descriptors
*/ */
__vic_init(regs, -1, ~0, ~0, node); __vic_init(regs, 0, ~0, ~0, node);
return 0; return 0;
} }
......
...@@ -841,8 +841,6 @@ config SOC_IMX6Q ...@@ -841,8 +841,6 @@ config SOC_IMX6Q
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select ARCH_HAS_OPP select ARCH_HAS_OPP
select ARM_CPU_SUSPEND if PM select ARM_CPU_SUSPEND if PM
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select ARM_ERRATA_754322 select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420 select ARM_ERRATA_775420
......
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
* IRQ interrupts definitions are the same as the INT definitions * IRQ interrupts definitions are the same as the INT definitions
* held within platform.h * held within platform.h
*/ */
#define IRQ_VIC_START 0 #define IRQ_VIC_START 32
#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
...@@ -100,7 +100,7 @@ ...@@ -100,7 +100,7 @@
/* /*
* Secondary interrupt controller * Secondary interrupt controller
*/ */
#define IRQ_SIC_START 32 #define IRQ_SIC_START 64
#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
...@@ -120,7 +120,7 @@ ...@@ -120,7 +120,7 @@
#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
#define IRQ_SIC_END 63 #define IRQ_SIC_END 95
#define IRQ_GPIO0_START (IRQ_SIC_END + 1) #define IRQ_GPIO0_START (IRQ_SIC_END + 1)
#define IRQ_GPIO0_END (IRQ_GPIO0_START + 31) #define IRQ_GPIO0_END (IRQ_GPIO0_START + 31)
......
...@@ -42,7 +42,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA ...@@ -42,7 +42,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
bool "Enable A5 and A9 only errata work-arounds" bool "Enable A5 and A9 only errata work-arounds"
default y default y
select ARM_ERRATA_720789 select ARM_ERRATA_720789
select ARM_ERRATA_751472
select PL310_ERRATA_753970 if CACHE_PL310 select PL310_ERRATA_753970 if CACHE_PL310
help help
Provides common dependencies for Versatile Express platforms Provides common dependencies for Versatile Express platforms
......
...@@ -352,7 +352,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) ...@@ -352,7 +352,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
/* Unmapped register. */ /* Unmapped register. */
sync_reg_offset = L2X0_DUMMY_REG; sync_reg_offset = L2X0_DUMMY_REG;
#endif #endif
outer_cache.set_debug = pl310_set_debug; if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
outer_cache.set_debug = pl310_set_debug;
break; break;
case L2X0_CACHE_ID_PART_L210: case L2X0_CACHE_ID_PART_L210:
ways = (aux >> 13) & 0xf; ways = (aux >> 13) & 0xf;
...@@ -459,8 +460,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end, ...@@ -459,8 +460,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end,
unsigned long flags; unsigned long flags;
raw_spin_lock_irqsave(&l2x0_lock, flags); raw_spin_lock_irqsave(&l2x0_lock, flags);
writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
writel(end, l2x0_base + offset); writel_relaxed(end, l2x0_base + offset);
raw_spin_unlock_irqrestore(&l2x0_lock, flags); raw_spin_unlock_irqrestore(&l2x0_lock, flags);
cache_sync(); cache_sync();
...@@ -505,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end) ...@@ -505,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
static void aurora_flush_range(unsigned long start, unsigned long end) static void aurora_flush_range(unsigned long start, unsigned long end)
{ {
if (!l2_wt_override) { start &= ~(CACHE_LINE_SIZE - 1);
start &= ~(CACHE_LINE_SIZE - 1); end = ALIGN(end, CACHE_LINE_SIZE);
end = ALIGN(end, CACHE_LINE_SIZE); while (start != end) {
while (start != end) { unsigned long range_end = calc_range_end(start, end);
unsigned long range_end = calc_range_end(start, end); /*
* If L2 is forced to WT, the L2 will always be clean and we
* just need to invalidate.
*/
if (l2_wt_override)
aurora_pa_range(start, range_end - CACHE_LINE_SIZE, aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
AURORA_FLUSH_RANGE_REG); AURORA_INVAL_RANGE_REG);
start = range_end; else
} aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
AURORA_FLUSH_RANGE_REG);
start = range_end;
} }
} }
...@@ -668,8 +675,9 @@ static void pl310_resume(void) ...@@ -668,8 +675,9 @@ static void pl310_resume(void)
static void aurora_resume(void) static void aurora_resume(void)
{ {
if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL); writel_relaxed(l2x0_saved_regs.aux_ctrl,
writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); l2x0_base + L2X0_AUX_CTRL);
writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
} }
} }
......
...@@ -169,6 +169,7 @@ __v7_ca15mp_setup: ...@@ -169,6 +169,7 @@ __v7_ca15mp_setup:
orreq r0, r0, r10 @ Enable CPU-specific SMP bits orreq r0, r0, r10 @ Enable CPU-specific SMP bits
mcreq p15, 0, r0, c1, c0, 1 mcreq p15, 0, r0, c1, c0, 1
#endif #endif
b __v7_setup
__v7_pj4b_setup: __v7_pj4b_setup:
#ifdef CONFIG_CPU_PJ4B #ifdef CONFIG_CPU_PJ4B
...@@ -245,7 +246,8 @@ __v7_setup: ...@@ -245,7 +246,8 @@ __v7_setup:
ldr r10, =0x00000c08 @ Cortex-A8 primary part number ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10 teq r0, r10
bne 2f bne 2f
#ifdef CONFIG_ARM_ERRATA_430973 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
teq r5, #0x00100000 @ only present in r1p* teq r5, #0x00100000 @ only present in r1p*
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
orreq r10, r10, #(1 << 6) @ set IBE to 1 orreq r10, r10, #(1 << 6) @ set IBE to 1
......
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