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Commit 5f152a57 authored by Alex Deucher's avatar Alex Deucher
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drm/radeon: use pcie functions for link width 

This is the last user of drm_pcie_get_speed_cap_mask.  Use the pci
version so we can drop drm_pcie_get_speed_cap_mask.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5d9a6330
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Showing with 60 additions and 32 deletions
drivers/gpu/drm/radeon/ci_dpm.c
View file @ 5f152a57
...@@ -5676,19 +5676,29 @@ int ci_dpm_init(struct radeon_device *rdev) ...@@ -5676,19 +5676,29 @@ int ci_dpm_init(struct radeon_device *rdev)
u16 data_offset, size; u16 data_offset, size;
u8 frev, crev; u8 frev, crev;
struct ci_power_info *pi; struct ci_power_info *pi;
enum pci_bus_speed speed_cap;
struct pci_dev *root = rdev->pdev->bus->self;
int ret; int ret;
u32 mask;
pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
if (pi == NULL) if (pi == NULL)
return -ENOMEM; return -ENOMEM;
rdev->pm.dpm.priv = pi; rdev->pm.dpm.priv = pi;
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); speed_cap = pcie_get_speed_cap(root);
if (ret) if (speed_cap == PCI_SPEED_UNKNOWN) {
pi->sys_pcie_mask = 0; pi->sys_pcie_mask = 0;
else } else {
pi->sys_pcie_mask = mask; if (speed_cap == PCIE_SPEED_8_0GT)
pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
RADEON_PCIE_SPEED_50 |
RADEON_PCIE_SPEED_80;
else if (speed_cap == PCIE_SPEED_5_0GT)
pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
RADEON_PCIE_SPEED_50;
else
pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
}
pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
......
drivers/gpu/drm/radeon/cik.c
View file @ 5f152a57
...@@ -9499,9 +9499,10 @@ int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) ...@@ -9499,9 +9499,10 @@ int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
static void cik_pcie_gen3_enable(struct radeon_device *rdev) static void cik_pcie_gen3_enable(struct radeon_device *rdev)
{ {
struct pci_dev *root = rdev->pdev->bus->self; struct pci_dev *root = rdev->pdev->bus->self;
enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos; int bridge_pos, gpu_pos;
u32 speed_cntl, mask, current_data_rate; u32 speed_cntl, current_data_rate;
int ret, i; int i;
u16 tmp16; u16 tmp16;
if (pci_is_root_bus(rdev->pdev->bus)) if (pci_is_root_bus(rdev->pdev->bus))
...@@ -9516,23 +9517,24 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) ...@@ -9516,23 +9517,24 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
if (!(rdev->flags & RADEON_IS_PCIE)) if (!(rdev->flags & RADEON_IS_PCIE))
return; return;
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); speed_cap = pcie_get_speed_cap(root);
if (ret != 0) if (speed_cap == PCI_SPEED_UNKNOWN)
return; return;
if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) if ((speed_cap != PCIE_SPEED_8_0GT) &&
(speed_cap != PCIE_SPEED_5_0GT))
return; return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
LC_CURRENT_DATA_RATE_SHIFT; LC_CURRENT_DATA_RATE_SHIFT;
if (mask & DRM_PCIE_SPEED_80) { if (speed_cap == PCIE_SPEED_8_0GT) {
if (current_data_rate == 2) { if (current_data_rate == 2) {
DRM_INFO("PCIE gen 3 link speeds already enabled\n"); DRM_INFO("PCIE gen 3 link speeds already enabled\n");
return; return;
} }
DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
} else if (mask & DRM_PCIE_SPEED_50) { } else if (speed_cap == PCIE_SPEED_5_0GT) {
if (current_data_rate == 1) { if (current_data_rate == 1) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n"); DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return; return;
...@@ -9548,7 +9550,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) ...@@ -9548,7 +9550,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
if (!gpu_pos) if (!gpu_pos)
return; return;
if (mask & DRM_PCIE_SPEED_80) { if (speed_cap == PCIE_SPEED_8_0GT) {
/* re-try equalization if gen3 is not already enabled */ /* re-try equalization if gen3 is not already enabled */
if (current_data_rate != 2) { if (current_data_rate != 2) {
u16 bridge_cfg, gpu_cfg; u16 bridge_cfg, gpu_cfg;
...@@ -9636,9 +9638,9 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) ...@@ -9636,9 +9638,9 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf; tmp16 &= ~0xf;
if (mask & DRM_PCIE_SPEED_80) if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */ tmp16 |= 3; /* gen3 */
else if (mask & DRM_PCIE_SPEED_50) else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */ tmp16 |= 2; /* gen2 */
else else
tmp16 |= 1; /* gen1 */ tmp16 |= 1; /* gen1 */
......
drivers/gpu/drm/radeon/r600_dpm.c
View file @ 5f152a57
...@@ -1327,9 +1327,9 @@ enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev, ...@@ -1327,9 +1327,9 @@ enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
case RADEON_PCIE_GEN3: case RADEON_PCIE_GEN3:
return RADEON_PCIE_GEN3; return RADEON_PCIE_GEN3;
default: default:
if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3)) if ((sys_mask & RADEON_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
return RADEON_PCIE_GEN3; return RADEON_PCIE_GEN3;
else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2)) else if ((sys_mask & RADEON_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
return RADEON_PCIE_GEN2; return RADEON_PCIE_GEN2;
else else
return RADEON_PCIE_GEN1; return RADEON_PCIE_GEN1;
......
drivers/gpu/drm/radeon/radeon.h
View file @ 5f152a57
...@@ -1653,6 +1653,10 @@ struct radeon_pm { ...@@ -1653,6 +1653,10 @@ struct radeon_pm {
struct radeon_dpm dpm; struct radeon_dpm dpm;
}; };
#define RADEON_PCIE_SPEED_25 1
#define RADEON_PCIE_SPEED_50 2
#define RADEON_PCIE_SPEED_80 4
int radeon_pm_get_type_index(struct radeon_device *rdev, int radeon_pm_get_type_index(struct radeon_device *rdev,
enum radeon_pm_state_type ps_type, enum radeon_pm_state_type ps_type,
int instance); int instance);
......
drivers/gpu/drm/radeon/si.c
View file @ 5f152a57
...@@ -7082,9 +7082,10 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) ...@@ -7082,9 +7082,10 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
static void si_pcie_gen3_enable(struct radeon_device *rdev) static void si_pcie_gen3_enable(struct radeon_device *rdev)
{ {
struct pci_dev *root = rdev->pdev->bus->self; struct pci_dev *root = rdev->pdev->bus->self;
enum pci_bus_speed speed_cap;
int bridge_pos, gpu_pos; int bridge_pos, gpu_pos;
u32 speed_cntl, mask, current_data_rate; u32 speed_cntl, current_data_rate;
int ret, i; int i;
u16 tmp16; u16 tmp16;
if (pci_is_root_bus(rdev->pdev->bus)) if (pci_is_root_bus(rdev->pdev->bus))
...@@ -7099,23 +7100,24 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) ...@@ -7099,23 +7100,24 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
if (!(rdev->flags & RADEON_IS_PCIE)) if (!(rdev->flags & RADEON_IS_PCIE))
return; return;
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); speed_cap = pcie_get_speed_cap(root);
if (ret != 0) if (speed_cap == PCI_SPEED_UNKNOWN)
return; return;
if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) if ((speed_cap != PCIE_SPEED_8_0GT) &&
(speed_cap != PCIE_SPEED_5_0GT))
return; return;
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
LC_CURRENT_DATA_RATE_SHIFT; LC_CURRENT_DATA_RATE_SHIFT;
if (mask & DRM_PCIE_SPEED_80) { if (speed_cap == PCIE_SPEED_8_0GT) {
if (current_data_rate == 2) { if (current_data_rate == 2) {
DRM_INFO("PCIE gen 3 link speeds already enabled\n"); DRM_INFO("PCIE gen 3 link speeds already enabled\n");
return; return;
} }
DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"); DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
} else if (mask & DRM_PCIE_SPEED_50) { } else if (speed_cap == PCIE_SPEED_5_0GT) {
if (current_data_rate == 1) { if (current_data_rate == 1) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n"); DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return; return;
...@@ -7131,7 +7133,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) ...@@ -7131,7 +7133,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
if (!gpu_pos) if (!gpu_pos)
return; return;
if (mask & DRM_PCIE_SPEED_80) { if (speed_cap == PCIE_SPEED_8_0GT) {
/* re-try equalization if gen3 is not already enabled */ /* re-try equalization if gen3 is not already enabled */
if (current_data_rate != 2) { if (current_data_rate != 2) {
u16 bridge_cfg, gpu_cfg; u16 bridge_cfg, gpu_cfg;
...@@ -7219,9 +7221,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) ...@@ -7219,9 +7221,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
tmp16 &= ~0xf; tmp16 &= ~0xf;
if (mask & DRM_PCIE_SPEED_80) if (speed_cap == PCIE_SPEED_8_0GT)
tmp16 |= 3; /* gen3 */ tmp16 |= 3; /* gen3 */
else if (mask & DRM_PCIE_SPEED_50) else if (speed_cap == PCIE_SPEED_5_0GT)
tmp16 |= 2; /* gen2 */ tmp16 |= 2; /* gen2 */
else else
tmp16 |= 1; /* gen1 */ tmp16 |= 1; /* gen1 */
......
drivers/gpu/drm/radeon/si_dpm.c
View file @ 5f152a57
...@@ -6899,8 +6899,9 @@ int si_dpm_init(struct radeon_device *rdev) ...@@ -6899,8 +6899,9 @@ int si_dpm_init(struct radeon_device *rdev)
struct ni_power_info *ni_pi; struct ni_power_info *ni_pi;
struct si_power_info *si_pi; struct si_power_info *si_pi;
struct atom_clock_dividers dividers; struct atom_clock_dividers dividers;
enum pci_bus_speed speed_cap;
struct pci_dev *root = rdev->pdev->bus->self;
int ret; int ret;
u32 mask;
si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
if (si_pi == NULL) if (si_pi == NULL)
...@@ -6910,11 +6911,20 @@ int si_dpm_init(struct radeon_device *rdev) ...@@ -6910,11 +6911,20 @@ int si_dpm_init(struct radeon_device *rdev)
eg_pi = &ni_pi->eg; eg_pi = &ni_pi->eg;
pi = &eg_pi->rv7xx; pi = &eg_pi->rv7xx;
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); speed_cap = pcie_get_speed_cap(root);
if (ret) if (speed_cap == PCI_SPEED_UNKNOWN) {
si_pi->sys_pcie_mask = 0; si_pi->sys_pcie_mask = 0;
else } else {
si_pi->sys_pcie_mask = mask; if (speed_cap == PCIE_SPEED_8_0GT)
si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
RADEON_PCIE_SPEED_50 |
RADEON_PCIE_SPEED_80;
else if (speed_cap == PCIE_SPEED_5_0GT)
si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
RADEON_PCIE_SPEED_50;
else
si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
}
si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
......
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