Commit 60661933 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Jeff Garzik

pata_hpt3x2n: always stretch UltraDMA timing

The UltraDMA Tss timing must be stretched with ATA clock of 66 MHz, but the
driver only does this when PCI clock is 66 MHz, whereas it always programs
DPLL clock (which is used as the ATA clock) to 66 MHz.
Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: <stable@kernel.org>
Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
parent 56f46f8c
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
#include <linux/libata.h> #include <linux/libata.h>
#define DRV_NAME "pata_hpt3x2n" #define DRV_NAME "pata_hpt3x2n"
#define DRV_VERSION "0.3.8" #define DRV_VERSION "0.3.9"
enum { enum {
HPT_PCI_FAST = (1 << 31), HPT_PCI_FAST = (1 << 31),
...@@ -544,16 +544,16 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) ...@@ -544,16 +544,16 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
pci_mhz); pci_mhz);
/* Set our private data up. We only need a few flags so we use /* Set our private data up. We only need a few flags so we use
it directly */ it directly */
if (pci_mhz > 60) { if (pci_mhz > 60)
hpriv = (void *)(PCI66 | USE_DPLL); hpriv = (void *)(PCI66 | USE_DPLL);
/*
* On HPT371N, if ATA clock is 66 MHz we must set bit 2 in /*
* the MISC. register to stretch the UltraDMA Tss timing. * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
* NOTE: This register is only writeable via I/O space. * the MISC. register to stretch the UltraDMA Tss timing.
*/ * NOTE: This register is only writeable via I/O space.
if (dev->device == PCI_DEVICE_ID_TTI_HPT371) */
outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
} outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
/* Now kick off ATA set up */ /* Now kick off ATA set up */
return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv); return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
......
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